416 lines
12 KiB
C
416 lines
12 KiB
C
/*
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* Copyright (c) 2001 Navin Boppuri / Prashant Patel
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* <nboppuri@trinetcommunication.com>,
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* <pmpatel@trinetcommunication.com>
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* Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
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* Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* MPC8260 CPM SPI interface.
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*
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* Parts of this code are probably not portable and/or specific to
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* the board which I used for the tests. Please send fixes/complaints
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* to wd@denx.de
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*
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*/
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#include <common.h>
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#include <asm/cpm_8260.h>
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#include <linux/ctype.h>
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#include <malloc.h>
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#include <post.h>
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#include <net.h>
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#if defined(CONFIG_SPI)
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/* Warning:
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* You cannot enable DEBUG for early system initalization, i. e. when
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* this driver is used to read environment parameters like "baudrate"
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* from EEPROM which are used to initialize the serial port which is
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* needed to print the debug messages...
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*/
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#undef DEBUG
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#define SPI_EEPROM_WREN 0x06
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#define SPI_EEPROM_RDSR 0x05
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#define SPI_EEPROM_READ 0x03
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#define SPI_EEPROM_WRITE 0x02
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/* ---------------------------------------------------------------
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* Offset for initial SPI buffers in DPRAM:
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* We need a 520 byte scratch DPRAM area to use at an early stage.
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* It is used between the two initialization calls (spi_init_f()
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* and spi_init_r()).
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* The value 0x2000 makes it far enough from the start of the data
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* area (as well as from the stack pointer).
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* --------------------------------------------------------------- */
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#ifndef CONFIG_SYS_SPI_INIT_OFFSET
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#define CONFIG_SYS_SPI_INIT_OFFSET 0x2000
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#endif
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#define CPM_SPI_BASE 0x100
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#ifdef DEBUG
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#define DPRINT(a) printf a;
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/* -----------------------------------------------
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* Helper functions to peek into tx and rx buffers
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* ----------------------------------------------- */
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static const char * const hex_digit = "0123456789ABCDEF";
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static char quickhex (int i)
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{
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return hex_digit[i];
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}
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static void memdump (void *pv, int num)
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{
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int i;
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unsigned char *pc = (unsigned char *) pv;
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for (i = 0; i < num; i++)
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printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
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printf ("\t");
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for (i = 0; i < num; i++)
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printf ("%c", isprint (pc[i]) ? pc[i] : '.');
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printf ("\n");
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}
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#else /* !DEBUG */
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#define DPRINT(a)
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#endif /* DEBUG */
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/* -------------------
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* Function prototypes
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* ------------------- */
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void spi_init (void);
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ssize_t spi_read (uchar *, int, uchar *, int);
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ssize_t spi_write (uchar *, int, uchar *, int);
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ssize_t spi_xfer (size_t);
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/* -------------------
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* Variables
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* ------------------- */
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#define MAX_BUFFER 0x104
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/* ----------------------------------------------------------------------
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* Initially we place the RX and TX buffers at a fixed location in DPRAM!
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* ---------------------------------------------------------------------- */
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static uchar *rxbuf =
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(uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase
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[CONFIG_SYS_SPI_INIT_OFFSET];
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static uchar *txbuf =
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(uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase
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[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
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/* **************************************************************************
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*
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* Function: spi_init_f
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*
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* Description: Init SPI-Controller (ROM part)
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*
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* return: ---
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*
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* *********************************************************************** */
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void spi_init_f (void)
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{
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unsigned int dpaddr;
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volatile spi_t *spi;
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volatile immap_t *immr;
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volatile cpm8260_t *cp;
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volatile cbd_t *tbdf, *rbdf;
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immr = (immap_t *) CONFIG_SYS_IMMR;
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cp = (cpm8260_t *) &immr->im_cpm;
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immr->im_dprambase16[PROFF_SPI_BASE / sizeof(u16)] = PROFF_SPI;
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spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
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/* 1 */
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/* ------------------------------------------------
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* Initialize Port D SPI pins
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* (we are only in Master Mode !)
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* ------------------------------------------------ */
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/* --------------------------------------------
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* GPIO or per. Function
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* PPARD[16] = 1 [0x00008000] (SPIMISO)
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* PPARD[17] = 1 [0x00004000] (SPIMOSI)
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* PPARD[18] = 1 [0x00002000] (SPICLK)
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* PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM)
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* -------------------------------------------- */
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immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */
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immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */
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/* ----------------------------------------------
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* In/Out or per. Function 0/1
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* PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO
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* PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI
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* PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK
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* PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM
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* ---------------------------------------------- */
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immr->im_ioport.iop_pdird &= ~0x0000E000;
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immr->im_ioport.iop_pdird |= 0x00080000;
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/* ----------------------------------------------
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* special option reg.
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* PSORD[16] = 1 [0x00008000] -> SPIMISO
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* PSORD[17] = 1 [0x00004000] -> SPIMOSI
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* PSORD[18] = 1 [0x00002000] -> SPICLK
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* ---------------------------------------------- */
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immr->im_ioport.iop_psord |= 0x0000E000;
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/* Initialize the parameter ram.
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* We need to make sure many things are initialized to zero
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*/
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spi->spi_rstate = 0;
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spi->spi_rdp = 0;
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spi->spi_rbptr = 0;
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spi->spi_rbc = 0;
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spi->spi_rxtmp = 0;
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spi->spi_tstate = 0;
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spi->spi_tdp = 0;
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spi->spi_tbptr = 0;
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spi->spi_tbc = 0;
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spi->spi_txtmp = 0;
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/* Allocate space for one transmit and one receive buffer
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* descriptor in the DP ram
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*/
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#ifdef CONFIG_SYS_ALLOC_DPRAM
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dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8);
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#else
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dpaddr = CPM_SPI_BASE;
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#endif
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/* 3 */
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/* Set up the SPI parameters in the parameter ram */
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spi->spi_rbase = dpaddr;
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spi->spi_tbase = dpaddr + sizeof (cbd_t);
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/***********IMPORTANT******************/
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/*
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* Setting transmit and receive buffer descriptor pointers
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* initially to rbase and tbase. Only the microcode patches
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* documentation talks about initializing this pointer. This
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* is missing from the sample I2C driver. If you dont
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* initialize these pointers, the kernel hangs.
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*/
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spi->spi_rbptr = spi->spi_rbase;
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spi->spi_tbptr = spi->spi_tbase;
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/* 4 */
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/* Init SPI Tx + Rx Parameters */
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while (cp->cp_cpcr & CPM_CR_FLG)
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;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK,
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0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG)
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;
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/* 6 */
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/* Set to big endian. */
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spi->spi_tfcr = CPMFCR_EB;
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spi->spi_rfcr = CPMFCR_EB;
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/* 7 */
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/* Set maximum receive size. */
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spi->spi_mrblr = MAX_BUFFER;
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/* 8 + 9 */
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/* tx and rx buffer descriptors */
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tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
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rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
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tbdf->cbd_sc &= ~BD_SC_READY;
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rbdf->cbd_sc &= ~BD_SC_EMPTY;
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/* Set the bd's rx and tx buffer address pointers */
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rbdf->cbd_bufaddr = (ulong) rxbuf;
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tbdf->cbd_bufaddr = (ulong) txbuf;
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/* 10 + 11 */
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immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */
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immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */
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return;
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}
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/* **************************************************************************
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*
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* Function: spi_init_r
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*
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* Description: Init SPI-Controller (RAM part) -
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* The malloc engine is ready and we can move our buffers to
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* normal RAM
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*
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* return: ---
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*
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* *********************************************************************** */
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void spi_init_r (void)
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{
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volatile spi_t *spi;
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volatile immap_t *immr;
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volatile cbd_t *tbdf, *rbdf;
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immr = (immap_t *) CONFIG_SYS_IMMR;
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spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
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/* tx and rx buffer descriptors */
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tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
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rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
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/* Allocate memory for RX and TX buffers */
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rxbuf = (uchar *) malloc (MAX_BUFFER);
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txbuf = (uchar *) malloc (MAX_BUFFER);
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rbdf->cbd_bufaddr = (ulong) rxbuf;
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tbdf->cbd_bufaddr = (ulong) txbuf;
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return;
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}
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/****************************************************************************
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* Function: spi_write
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**************************************************************************** */
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ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
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{
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int i;
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memset(rxbuf, 0, MAX_BUFFER);
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memset(txbuf, 0, MAX_BUFFER);
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*txbuf = SPI_EEPROM_WREN; /* write enable */
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spi_xfer(1);
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memcpy(txbuf, addr, alen);
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*txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
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memcpy(alen + txbuf, buffer, len);
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spi_xfer(alen + len);
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/* ignore received data */
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for (i = 0; i < 1000; i++) {
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*txbuf = SPI_EEPROM_RDSR; /* read status */
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txbuf[1] = 0;
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spi_xfer(2);
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if (!(rxbuf[1] & 1)) {
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break;
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}
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udelay(1000);
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}
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if (i >= 1000) {
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printf ("*** spi_write: Time out while writing!\n");
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}
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return len;
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}
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/****************************************************************************
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* Function: spi_read
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**************************************************************************** */
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ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
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{
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memset(rxbuf, 0, MAX_BUFFER);
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memset(txbuf, 0, MAX_BUFFER);
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memcpy(txbuf, addr, alen);
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*txbuf = SPI_EEPROM_READ; /* READ memory array */
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/*
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* There is a bug in 860T (?) that cuts the last byte of input
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* if we're reading into DPRAM. The solution we choose here is
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* to always read len+1 bytes (we have one extra byte at the
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* end of the buffer).
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*/
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spi_xfer(alen + len + 1);
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memcpy(buffer, alen + rxbuf, len);
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return len;
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}
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/****************************************************************************
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* Function: spi_xfer
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**************************************************************************** */
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ssize_t spi_xfer (size_t count)
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{
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volatile immap_t *immr;
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volatile spi_t *spi;
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cbd_t *tbdf, *rbdf;
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int tm;
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DPRINT (("*** spi_xfer entered ***\n"));
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immr = (immap_t *) CONFIG_SYS_IMMR;
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spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
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tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
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rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
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/* Board-specific: Set CS for device (ATC EEPROM) */
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immr->im_ioport.iop_pdatd &= ~0x00080000;
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/* Setting tx bd status and data length */
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tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
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tbdf->cbd_datlen = count;
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DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n",
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tbdf->cbd_datlen));
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/* Setting rx bd status and data length */
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rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
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rbdf->cbd_datlen = 0; /* rx length has no significance */
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immr->im_spi.spi_spmode = SPMODE_REV |
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SPMODE_MSTR |
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SPMODE_EN |
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SPMODE_LEN(8) | /* 8 Bits per char */
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SPMODE_PM(0x8) ; /* medium speed */
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immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */
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immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */
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/* start spi transfer */
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DPRINT (("*** spi_xfer: Performing transfer ...\n"));
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immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */
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/* --------------------------------
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* -------------------------------- */
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for (tm=0; tm<1000; ++tm) {
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if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */
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DPRINT (("*** spi_xfer: Tx buffer empty\n"));
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break;
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}
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if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
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DPRINT (("*** spi_xfer: Tx BD done\n"));
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break;
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}
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udelay (1000);
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}
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if (tm >= 1000) {
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printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
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}
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DPRINT (("*** spi_xfer: ... transfer ended\n"));
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#ifdef DEBUG
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printf ("\nspi_xfer: txbuf after xfer\n");
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memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */
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printf ("spi_xfer: rxbuf after xfer\n");
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memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */
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printf ("\n");
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#endif
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/* Clear CS for device */
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immr->im_ioport.iop_pdatd |= 0x00080000;
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return count;
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}
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#endif /* CONFIG_SPI */
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