720 lines
15 KiB
C
720 lines
15 KiB
C
/*
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* (C) Copyright 2000-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPU specific code
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*
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* written or collected and sometimes rewritten by
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* Magnus Damm <damm@bitsmart.com>
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*
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* minor modifications by
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* Wolfgang Denk <wd@denx.de>
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <asm/ppc4xx.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_reset(void);
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/*
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* To provide an interface to detect CPU number for boards that support
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* more then one CPU, we implement the "weak" default functions here.
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*
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* Returns CPU number
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*/
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int __get_cpu_num(void)
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{
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return NA_OR_UNKNOWN_CPU;
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}
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int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
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#if defined(CONFIG_PCI)
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#if defined(CONFIG_405GP) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define PCI_ASYNC
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static int pci_async_enabled(void)
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{
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#if defined(CONFIG_405GP)
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return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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unsigned long val;
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mfsdr(SDR0_SDSTP1, val);
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return (val & SDR0_SDSTP1_PAME_MASK);
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#endif
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}
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#endif
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_PCI) && \
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!defined(CONFIG_405) && !defined(CONFIG_405EX)
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int pci_arbiter_enabled(void)
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{
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#if defined(CONFIG_405GP)
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return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
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#endif
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#if defined(CONFIG_405EP)
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return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
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#endif
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#if defined(CONFIG_440GP)
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return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
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#endif
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#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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unsigned long val;
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mfsdr(SDR0_XCR0, val);
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return (val & SDR0_XCR0_PAE_MASK);
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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unsigned long val;
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mfsdr(SDR0_PCI0, val);
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return (val & SDR0_PCI0_PAE_MASK);
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#endif
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}
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#endif
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#if defined(CONFIG_405EP)
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#define I2C_BOOTROM
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static int i2c_bootrom_enabled(void)
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{
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#if defined(CONFIG_405EP)
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return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
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#else
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unsigned long val;
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mfsdr(SDR0_SDCS0, val);
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return (val & SDR0_SDCS_SDD);
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#endif
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}
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#endif
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#if defined(CONFIG_440GX)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"EBC (16 bits)",
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"EBC (8 bits)",
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"EBC (32 bits)",
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"EBC (8 bits)",
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"PCI",
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"I2C (Addr 0x54)",
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"Reserved",
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"I2C (Addr 0x50)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
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#endif
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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#define SDR0_PINSTP_SHIFT 30
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"PCI",
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"I2C (Addr 0x54)",
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"I2C (Addr 0x50)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"PCI",
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"NAND (8 bits)",
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"EBC (16 bits)",
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"EBC (16 bits)",
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"I2C (Addr 0x54)",
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"PCI",
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"I2C (Addr 0x52)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
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#endif
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"EBC (16 bits)",
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"EBC (16 bits)",
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"NAND (8 bits)",
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"PCI",
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"I2C (Addr 0x54)",
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"PCI",
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"I2C (Addr 0x52)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
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#endif
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"EBC (16 bits)",
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"PCI",
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"PCI",
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"EBC (16 bits)",
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"NAND (8 bits)",
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"I2C (Addr 0x54)", /* A8 */
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"I2C (Addr 0x52)", /* A4 */
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
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#endif
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#if defined(CONFIG_460SX)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"EBC (16 bits)",
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"EBC (32 bits)",
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"NAND (8 bits)",
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"I2C (Addr 0x54)", /* A8 */
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"I2C (Addr 0x52)", /* A4 */
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
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#endif
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#if defined(CONFIG_405EZ)
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#define SDR0_PINSTP_SHIFT 28
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"SPI (fast)",
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"NAND (512 page, 4 addr cycle)",
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"I2C (Addr 0x50)",
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"EBC (32 bits)",
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"I2C (Addr 0x50)",
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"NAND (2K page, 5 addr cycle)",
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"I2C (Addr 0x50)",
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"EBC (16 bits)",
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"Reserved",
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"NAND (2K page, 4 addr cycle)",
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"I2C (Addr 0x50)",
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"NAND (512 page, 3 addr cycle)",
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"I2C (Addr 0x50)",
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"SPI (slow)",
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"I2C (Addr 0x50)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
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'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
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#endif
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#if defined(CONFIG_405EX)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"EBC (16 bits)",
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"EBC (16 bits)",
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"NAND (8 bits)",
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"NAND (8 bits)",
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"I2C (Addr 0x54)",
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"EBC (8 bits)",
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"I2C (Addr 0x52)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
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#endif
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#if defined(CONFIG_APM821XX)
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#define SDR0_PINSTP_SHIFT 29
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static char *bootstrap_str[] = {
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"RESERVED",
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"RESERVED",
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"RESERVED",
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"NAND (8 bits)",
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"NOR (8 bits)",
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"NOR (8 bits) w/PLL Bypassed",
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"I2C (Addr 0x54)",
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"I2C (Addr 0x52)",
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};
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static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
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#endif
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#if defined(SDR0_PINSTP_SHIFT)
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static int bootstrap_option(void)
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{
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unsigned long val;
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mfsdr(SDR0_PINSTP, val);
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return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
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}
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#endif /* SDR0_PINSTP_SHIFT */
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#if defined(CONFIG_440GP)
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static int do_chip_reset (unsigned long sys0, unsigned long sys1)
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{
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/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
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* reset.
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*/
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mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
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mtdcr (CPC0_SYS0, sys0);
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mtdcr (CPC0_SYS1, sys1);
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mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
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mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
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return 1;
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}
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#endif /* CONFIG_440GP */
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int checkcpu (void)
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{
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#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
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uint pvr = get_pvr();
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ulong clock = gd->cpu_clk;
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char buf[32];
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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u32 reg;
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#endif
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char addstr[64] = "";
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sys_info_t sys_info;
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int cpu_num;
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cpu_num = get_cpu_num();
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if (cpu_num >= 0)
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printf("CPU%d: ", cpu_num);
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else
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puts("CPU: ");
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get_sys_info(&sys_info);
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#if defined(CONFIG_XILINX_440)
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puts("IBM PowerPC ");
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#else
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puts("AMCC PowerPC ");
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#endif
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switch (pvr) {
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#if !defined(CONFIG_440)
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case PVR_405GP_RB:
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puts("405GP Rev. B");
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break;
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case PVR_405GP_RC:
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puts("405GP Rev. C");
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break;
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case PVR_405GP_RD:
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puts("405GP Rev. D");
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break;
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case PVR_405GP_RE:
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puts("405GP Rev. E");
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break;
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case PVR_405GPR_RB:
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puts("405GPr Rev. B");
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break;
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case PVR_405EP_RB:
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puts("405EP Rev. B");
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break;
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case PVR_405EZ_RA:
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puts("405EZ Rev. A");
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break;
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case PVR_405EX1_RA:
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puts("405EX Rev. A");
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strcpy(addstr, "Security support");
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break;
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case PVR_405EXR2_RA:
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puts("405EXr Rev. A");
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strcpy(addstr, "No Security support");
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break;
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case PVR_405EX1_RC:
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puts("405EX Rev. C");
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strcpy(addstr, "Security support");
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break;
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case PVR_405EX2_RC:
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puts("405EX Rev. C");
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strcpy(addstr, "No Security support");
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break;
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case PVR_405EXR1_RC:
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puts("405EXr Rev. C");
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strcpy(addstr, "Security support");
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break;
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case PVR_405EXR2_RC:
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puts("405EXr Rev. C");
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strcpy(addstr, "No Security support");
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break;
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case PVR_405EX1_RD:
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puts("405EX Rev. D");
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strcpy(addstr, "Security support");
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break;
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case PVR_405EX2_RD:
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puts("405EX Rev. D");
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strcpy(addstr, "No Security support");
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break;
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case PVR_405EXR1_RD:
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puts("405EXr Rev. D");
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strcpy(addstr, "Security support");
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break;
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case PVR_405EXR2_RD:
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puts("405EXr Rev. D");
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strcpy(addstr, "No Security support");
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break;
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#else /* CONFIG_440 */
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#if defined(CONFIG_440GP)
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case PVR_440GP_RB:
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puts("440GP Rev. B");
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/* See errata 1.12: CHIP_4 */
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if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
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(mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
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puts ( "\n\t CPC0_SYSx DCRs corrupted. "
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"Resetting chip ...\n");
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udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
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do_chip_reset ( mfdcr(CPC0_STRP0),
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mfdcr(CPC0_STRP1) );
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}
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break;
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case PVR_440GP_RC:
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puts("440GP Rev. C");
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break;
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#endif /* CONFIG_440GP */
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case PVR_440GX_RA:
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puts("440GX Rev. A");
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break;
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case PVR_440GX_RB:
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puts("440GX Rev. B");
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break;
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case PVR_440GX_RC:
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puts("440GX Rev. C");
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break;
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case PVR_440GX_RF:
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puts("440GX Rev. F");
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break;
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case PVR_440EP_RA:
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puts("440EP Rev. A");
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break;
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#ifdef CONFIG_440EP
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case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
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puts("440EP Rev. B");
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break;
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case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
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puts("440EP Rev. C");
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break;
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#endif /* CONFIG_440EP */
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#ifdef CONFIG_440GR
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case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
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puts("440GR Rev. A");
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break;
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case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
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puts("440GR Rev. B");
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break;
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#endif /* CONFIG_440GR */
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#ifdef CONFIG_440EPX
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case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
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puts("440EPx Rev. A");
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strcpy(addstr, "Security/Kasumi support");
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break;
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case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
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puts("440EPx Rev. A");
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strcpy(addstr, "No Security/Kasumi support");
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break;
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#endif /* CONFIG_440EPX */
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#ifdef CONFIG_440GRX
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case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
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puts("440GRx Rev. A");
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strcpy(addstr, "Security/Kasumi support");
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break;
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case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
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puts("440GRx Rev. A");
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strcpy(addstr, "No Security/Kasumi support");
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break;
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#endif /* CONFIG_440GRX */
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case PVR_440SP_6_RAB:
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puts("440SP Rev. A/B");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SP_RAB:
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puts("440SP Rev. A/B");
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strcpy(addstr, "No RAID 6 support");
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break;
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case PVR_440SP_6_RC:
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puts("440SP Rev. C");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SP_RC:
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puts("440SP Rev. C");
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strcpy(addstr, "No RAID 6 support");
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break;
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case PVR_440SPe_6_RA:
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puts("440SPe Rev. A");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SPe_RA:
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puts("440SPe Rev. A");
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strcpy(addstr, "No RAID 6 support");
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break;
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case PVR_440SPe_6_RB:
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puts("440SPe Rev. B");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SPe_RB:
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puts("440SPe Rev. B");
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strcpy(addstr, "No RAID 6 support");
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break;
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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case PVR_460EX_RA:
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puts("460EX Rev. A");
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strcpy(addstr, "No Security/Kasumi support");
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break;
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case PVR_460EX_SE_RA:
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puts("460EX Rev. A");
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strcpy(addstr, "Security/Kasumi support");
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break;
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case PVR_460EX_RB:
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puts("460EX Rev. B");
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mfsdr(SDR0_ECID3, reg);
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|
if (reg & 0x00100000)
|
|
strcpy(addstr, "No Security/Kasumi support");
|
|
else
|
|
strcpy(addstr, "Security/Kasumi support");
|
|
break;
|
|
|
|
case PVR_460GT_RA:
|
|
puts("460GT Rev. A");
|
|
strcpy(addstr, "No Security/Kasumi support");
|
|
break;
|
|
|
|
case PVR_460GT_SE_RA:
|
|
puts("460GT Rev. A");
|
|
strcpy(addstr, "Security/Kasumi support");
|
|
break;
|
|
|
|
case PVR_460GT_RB:
|
|
puts("460GT Rev. B");
|
|
mfsdr(SDR0_ECID3, reg);
|
|
if (reg & 0x00100000)
|
|
strcpy(addstr, "No Security/Kasumi support");
|
|
else
|
|
strcpy(addstr, "Security/Kasumi support");
|
|
break;
|
|
#endif
|
|
|
|
case PVR_460SX_RA:
|
|
puts("460SX Rev. A");
|
|
strcpy(addstr, "Security support");
|
|
break;
|
|
|
|
case PVR_460SX_RA_V1:
|
|
puts("460SX Rev. A");
|
|
strcpy(addstr, "No Security support");
|
|
break;
|
|
|
|
case PVR_460GX_RA:
|
|
puts("460GX Rev. A");
|
|
strcpy(addstr, "Security support");
|
|
break;
|
|
|
|
case PVR_460GX_RA_V1:
|
|
puts("460GX Rev. A");
|
|
strcpy(addstr, "No Security support");
|
|
break;
|
|
|
|
case PVR_APM821XX_RA:
|
|
puts("APM821XX Rev. A");
|
|
strcpy(addstr, "Security support");
|
|
break;
|
|
|
|
case PVR_VIRTEX5:
|
|
puts("440x5 VIRTEX5");
|
|
break;
|
|
#endif /* CONFIG_440 */
|
|
|
|
default:
|
|
printf (" UNKNOWN (PVR=%08x)", pvr);
|
|
break;
|
|
}
|
|
|
|
printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
|
|
strmhz(buf, clock),
|
|
sys_info.freqPLB / 1000000,
|
|
get_OPB_freq() / 1000000,
|
|
sys_info.freqEBC / 1000000);
|
|
#if defined(CONFIG_PCI) && \
|
|
(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
|
|
defined(CONFIG_440GR) || defined(CONFIG_440GRX))
|
|
printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
|
|
#endif
|
|
printf(")\n");
|
|
|
|
if (addstr[0] != 0)
|
|
printf(" %s\n", addstr);
|
|
|
|
#if defined(I2C_BOOTROM)
|
|
printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
|
|
#endif /* I2C_BOOTROM */
|
|
#if defined(SDR0_PINSTP_SHIFT)
|
|
printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
|
|
printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
|
|
#ifdef CONFIG_NAND_U_BOOT
|
|
puts(", booting from NAND");
|
|
#endif /* CONFIG_NAND_U_BOOT */
|
|
putc('\n');
|
|
#endif /* SDR0_PINSTP_SHIFT */
|
|
|
|
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
|
|
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
|
|
if (pci_async_enabled()) {
|
|
printf (", PCI async ext clock used");
|
|
} else {
|
|
printf (", PCI sync clock at %lu MHz",
|
|
sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
|
|
putc('\n');
|
|
#endif
|
|
|
|
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
|
|
printf(" 16 KiB I-Cache 16 KiB D-Cache");
|
|
#elif defined(CONFIG_440)
|
|
printf(" 32 KiB I-Cache 32 KiB D-Cache");
|
|
#else
|
|
printf(" 16 KiB I-Cache %d KiB D-Cache",
|
|
((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
|
|
#endif
|
|
|
|
#endif /* !defined(CONFIG_405) */
|
|
|
|
putc ('\n');
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ppc440spe_revB() {
|
|
unsigned int pvr;
|
|
|
|
pvr = get_pvr();
|
|
if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
#if defined(CONFIG_BOARD_RESET)
|
|
board_reset();
|
|
#else
|
|
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
|
|
mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
|
|
#else
|
|
/*
|
|
* Initiate system reset in debug control register DBCR
|
|
*/
|
|
mtspr(SPRN_DBCR0, 0x30000000);
|
|
#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
|
|
#endif /* defined(CONFIG_BOARD_RESET) */
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
/*
|
|
* Get timebase clock frequency
|
|
*/
|
|
unsigned long get_tbclk (void)
|
|
{
|
|
sys_info_t sys_info;
|
|
|
|
get_sys_info(&sys_info);
|
|
return (sys_info.freqProcessor);
|
|
}
|
|
|
|
|
|
#if defined(CONFIG_WATCHDOG)
|
|
void watchdog_reset(void)
|
|
{
|
|
int re_enable = disable_interrupts();
|
|
reset_4xx_watchdog();
|
|
if (re_enable) enable_interrupts();
|
|
}
|
|
|
|
void reset_4xx_watchdog(void)
|
|
{
|
|
/*
|
|
* Clear TSR(WIS) bit
|
|
*/
|
|
mtspr(SPRN_TSR, 0x40000000);
|
|
}
|
|
#endif /* CONFIG_WATCHDOG */
|
|
|
|
/*
|
|
* Initializes on-chip ethernet controllers.
|
|
* to override, implement board_eth_init()
|
|
*/
|
|
int cpu_eth_init(bd_t *bis)
|
|
{
|
|
#if defined(CONFIG_PPC4xx_EMAC)
|
|
ppc_4xx_eth_initialize(bis);
|
|
#endif
|
|
return 0;
|
|
}
|