69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* (C) Copyright 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dwmmc.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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static const struct socfpga_clock_manager *clock_manager_base =
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(void *)SOCFPGA_CLKMGR_ADDRESS;
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static const struct socfpga_system_manager *system_manager_base =
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(void *)SOCFPGA_SYSMGR_ADDRESS;
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static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
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static void socfpga_dwmci_clksel(struct dwmci_host *host)
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{
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unsigned int drvsel;
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unsigned int smplsel;
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/* Disable SDMMC clock. */
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clrbits_le32(&clock_manager_base->per_pll_en,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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/* Configures drv_sel and smpl_sel */
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drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
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smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
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debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
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writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
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&system_manager_base->sdmmcgrp_ctrl);
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debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
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readl(&system_manager_base->sdmmcgrp_ctrl));
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/* Enable SDMMC clock */
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setbits_le32(&clock_manager_base->per_pll_en,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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}
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int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
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{
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struct dwmci_host *host = NULL;
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host = calloc(sizeof(struct dwmci_host), 1);
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if (!host) {
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printf("dwmci_host calloc fail!\n");
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return -1;
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}
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host->name = SOCFPGA_NAME;
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host->ioaddr = (void *)regbase;
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host->buswidth = bus_width;
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host->clksel = socfpga_dwmci_clksel;
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host->dev_index = index;
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/* fixed clock divide by 4 which due to the SDMMC wrapper */
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host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
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host->fifoth_val = MSIZE(0x2) |
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RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
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TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
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return add_dwmci(host, host->bus_hz, 400000);
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}
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