305 lines
		
	
	
		
			7.0 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			305 lines
		
	
	
		
			7.0 KiB
		
	
	
	
		
			C
		
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * (C) Copyright 2009 SAMSUNG Electronics
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|  * Minkyu Kang <mk7.kang@samsung.com>
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|  * Heungjun Kim <riverful.kim@samsung.com>
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|  *
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|  * based on drivers/serial/s3c64xx.c
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|  */
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| 
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| #include <common.h>
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| #include <dm.h>
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| #include <errno.h>
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| #include <fdtdec.h>
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| #include <asm/global_data.h>
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| #include <linux/compiler.h>
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| #include <asm/io.h>
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| #if !CONFIG_IS_ENABLED(ARCH_APPLE)
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| #include <asm/arch/clk.h>
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| #endif
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| #include <asm/arch/uart.h>
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| #include <serial.h>
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| #include <clk.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| enum {
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| 	PORT_S5P = 0,
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| 	PORT_S5L
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| };
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| 
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| #define S5L_RX_FIFO_COUNT_SHIFT	0
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| #define S5L_RX_FIFO_COUNT_MASK	(0xf << S5L_RX_FIFO_COUNT_SHIFT)
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| #define S5L_RX_FIFO_FULL	(1 << 8)
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| #define S5L_TX_FIFO_COUNT_SHIFT	4
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| #define S5L_TX_FIFO_COUNT_MASK	(0xf << S5L_TX_FIFO_COUNT_SHIFT)
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| #define S5L_TX_FIFO_FULL	(1 << 9)
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| 
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| #define S5P_RX_FIFO_COUNT_SHIFT	0
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| #define S5P_RX_FIFO_COUNT_MASK	(0xff << S5P_RX_FIFO_COUNT_SHIFT)
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| #define S5P_RX_FIFO_FULL	(1 << 8)
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| #define S5P_TX_FIFO_COUNT_SHIFT	16
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| #define S5P_TX_FIFO_COUNT_MASK	(0xff << S5P_TX_FIFO_COUNT_SHIFT)
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| #define S5P_TX_FIFO_FULL	(1 << 24)
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| 
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| /* Information about a serial port */
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| struct s5p_serial_plat {
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| 	struct s5p_uart *reg;  /* address of registers in physical memory */
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| 	u8 reg_width;	/* register width */
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| 	u8 port_id;     /* uart port number */
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| 	u8 rx_fifo_count_shift;
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| 	u8 tx_fifo_count_shift;
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| 	u32 rx_fifo_count_mask;
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| 	u32 tx_fifo_count_mask;
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| 	u32 rx_fifo_full;
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| 	u32 tx_fifo_full;
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| };
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| 
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| /*
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|  * The coefficient, used to calculate the baudrate on S5P UARTs is
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|  * calculated as
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|  * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
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|  * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
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|  * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
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|  */
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| static const int udivslot[] = {
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| 	0,
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| 	0x0080,
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| 	0x0808,
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| 	0x0888,
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| 	0x2222,
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| 	0x4924,
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| 	0x4a52,
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| 	0x54aa,
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| 	0x5555,
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| 	0xd555,
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| 	0xd5d5,
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| 	0xddd5,
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| 	0xdddd,
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| 	0xdfdd,
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| 	0xdfdf,
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| 	0xffdf,
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| };
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| 
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| static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
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| {
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| 	/* enable FIFOs, auto clear Rx FIFO */
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| 	writel(0x3, &uart->ufcon);
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| 	writel(0, &uart->umcon);
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| 	/* 8N1 */
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| 	writel(0x3, &uart->ulcon);
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| 	/* No interrupts, no DMA, pure polling */
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| 	writel(0x245, &uart->ucon);
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| }
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| 
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| static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
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| 					   uint uclk, int baudrate)
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| {
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| 	u32 val;
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| 
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| 	val = uclk / baudrate;
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| 
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| 	writel(val / 16 - 1, &uart->ubrdiv);
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| 
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| 	if (s5p_uart_divslot())
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| 		writew(udivslot[val % 16], &uart->rest.slot);
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| 	else if (reg_width == 4)
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| 		writel(val % 16, &uart->rest.value);
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| 	else
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| 		writeb(val % 16, &uart->rest.value);
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| }
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| 
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| #ifndef CONFIG_SPL_BUILD
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| int s5p_serial_setbrg(struct udevice *dev, int baudrate)
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| {
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| 	struct s5p_serial_plat *plat = dev_get_plat(dev);
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| 	struct s5p_uart *const uart = plat->reg;
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| 	u32 uclk;
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| 
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| #if CONFIG_IS_ENABLED(CLK_EXYNOS) || CONFIG_IS_ENABLED(ARCH_APPLE)
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| 	struct clk clk;
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| 	u32 ret;
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| 
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| 	ret = clk_get_by_index(dev, 1, &clk);
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| 	if (ret < 0)
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| 		return ret;
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| 	uclk = clk_get_rate(&clk);
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| #else
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| 	uclk = get_uart_clk(plat->port_id);
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| #endif
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| 
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| 	s5p_serial_baud(uart, plat->reg_width, uclk, baudrate);
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| 
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| 	return 0;
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| }
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| 
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| static int s5p_serial_probe(struct udevice *dev)
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| {
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| 	struct s5p_serial_plat *plat = dev_get_plat(dev);
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| 	struct s5p_uart *const uart = plat->reg;
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| 
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| 	s5p_serial_init(uart);
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| 
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| 	return 0;
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| }
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| 
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| static int serial_err_check(const struct s5p_uart *const uart, int op)
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| {
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| 	unsigned int mask;
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| 
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| 	/*
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| 	 * UERSTAT
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| 	 * Break Detect	[3]
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| 	 * Frame Err	[2] : receive operation
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| 	 * Parity Err	[1] : receive operation
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| 	 * Overrun Err	[0] : receive operation
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| 	 */
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| 	if (op)
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| 		mask = 0x8;
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| 	else
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| 		mask = 0xf;
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| 
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| 	return readl(&uart->uerstat) & mask;
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| }
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| 
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| static int s5p_serial_getc(struct udevice *dev)
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| {
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| 	struct s5p_serial_plat *plat = dev_get_plat(dev);
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| 	struct s5p_uart *const uart = plat->reg;
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| 
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| 	if (!(readl(&uart->ufstat) & plat->rx_fifo_count_mask))
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| 		return -EAGAIN;
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| 
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| 	serial_err_check(uart, 0);
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| 	if (plat->reg_width == 4)
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| 		return (int)(readl(&uart->urxh) & 0xff);
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| 	else
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| 		return (int)(readb(&uart->urxh) & 0xff);
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| }
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| 
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| static int s5p_serial_putc(struct udevice *dev, const char ch)
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| {
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| 	struct s5p_serial_plat *plat = dev_get_plat(dev);
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| 	struct s5p_uart *const uart = plat->reg;
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| 
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| 	if (readl(&uart->ufstat) & plat->tx_fifo_full)
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| 		return -EAGAIN;
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| 
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| 	if (plat->reg_width == 4)
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| 		writel(ch, &uart->utxh);
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| 	else
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| 		writeb(ch, &uart->utxh);
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| 	serial_err_check(uart, 1);
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| 
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| 	return 0;
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| }
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| 
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| static int s5p_serial_pending(struct udevice *dev, bool input)
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| {
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| 	struct s5p_serial_plat *plat = dev_get_plat(dev);
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| 	struct s5p_uart *const uart = plat->reg;
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| 	uint32_t ufstat = readl(&uart->ufstat);
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| 
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| 	if (input) {
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| 		return (ufstat & plat->rx_fifo_count_mask) >>
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| 			plat->rx_fifo_count_shift;
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| 	} else {
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| 		return (ufstat & plat->tx_fifo_count_mask) >>
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| 			plat->tx_fifo_count_shift;
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| 	}
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| }
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| 
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| static int s5p_serial_of_to_plat(struct udevice *dev)
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| {
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| 	struct s5p_serial_plat *plat = dev_get_plat(dev);
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| 	const ulong port_type = dev_get_driver_data(dev);
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| 	fdt_addr_t addr;
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| 
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| 	addr = dev_read_addr(dev);
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| 	if (addr == FDT_ADDR_T_NONE)
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| 		return -EINVAL;
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| 
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| 	plat->reg = (struct s5p_uart *)addr;
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| 	plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
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| 	plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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| 					"id", dev_seq(dev));
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| 
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| 	if (port_type == PORT_S5L) {
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| 		plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
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| 		plat->rx_fifo_count_mask = S5L_RX_FIFO_COUNT_MASK;
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| 		plat->rx_fifo_full = S5L_RX_FIFO_FULL;
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| 		plat->tx_fifo_count_shift = S5L_TX_FIFO_COUNT_SHIFT;
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| 		plat->tx_fifo_count_mask = S5L_TX_FIFO_COUNT_MASK;
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| 		plat->tx_fifo_full = S5L_TX_FIFO_FULL;
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| 	} else {
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| 		plat->rx_fifo_count_shift = S5P_RX_FIFO_COUNT_SHIFT;
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| 		plat->rx_fifo_count_mask = S5P_RX_FIFO_COUNT_MASK;
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| 		plat->rx_fifo_full = S5P_RX_FIFO_FULL;
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| 		plat->tx_fifo_count_shift = S5P_TX_FIFO_COUNT_SHIFT;
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| 		plat->tx_fifo_count_mask = S5P_TX_FIFO_COUNT_MASK;
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| 		plat->tx_fifo_full = S5P_TX_FIFO_FULL;
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static const struct dm_serial_ops s5p_serial_ops = {
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| 	.putc = s5p_serial_putc,
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| 	.pending = s5p_serial_pending,
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| 	.getc = s5p_serial_getc,
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| 	.setbrg = s5p_serial_setbrg,
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| };
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| 
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| static const struct udevice_id s5p_serial_ids[] = {
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| 	{ .compatible = "samsung,exynos4210-uart",	.data = PORT_S5P },
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| 	{ .compatible = "apple,s5l-uart",		.data = PORT_S5L },
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| 	{ }
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| };
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| 
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| U_BOOT_DRIVER(serial_s5p) = {
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| 	.name	= "serial_s5p",
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| 	.id	= UCLASS_SERIAL,
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| 	.of_match = s5p_serial_ids,
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| 	.of_to_plat = s5p_serial_of_to_plat,
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| 	.plat_auto	= sizeof(struct s5p_serial_plat),
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| 	.probe = s5p_serial_probe,
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| 	.ops	= &s5p_serial_ops,
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| };
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| #endif
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| 
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| #ifdef CONFIG_DEBUG_UART_S5P
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| 
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| #include <debug_uart.h>
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| 
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| static inline void _debug_uart_init(void)
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| {
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| 	if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
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| 		return;
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| 
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| 	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
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| 
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| 	s5p_serial_init(uart);
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| #if CONFIG_IS_ENABLED(ARCH_APPLE)
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| 	s5p_serial_baud(uart, 4, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
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| #else
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| 	s5p_serial_baud(uart, 1, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
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| #endif
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| }
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| 
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| static inline void _debug_uart_putc(int ch)
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| {
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| 	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
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| 
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| #if CONFIG_IS_ENABLED(ARCH_APPLE)
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| 	while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
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| 	writel(ch, &uart->utxh);
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| #else
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| 	while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL);
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| 	writeb(ch, &uart->utxh);
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| #endif
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| }
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| 
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| DEBUG_UART_FUNCS
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| 
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| #endif
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