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u-boot/board/freescale/corenet_ds
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Timur Tabi a836626cc4 powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) 
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 		2011-10-20 16:01:37 -05:00
..
Makefile punt unused clean/distclean targets 2011-10-15 22:20:36 +02:00
corenet_ds.c powerpc/85xx: Cleanup extern in corenet_ds board code 2011-09-29 19:01:05 -05:00
corenet_ds.h powerpc/85xx: Cleanup extern in corenet_ds board code 2011-09-29 19:01:05 -05:00
ddr.c powerpc/mpc8xxx: Merge entries in DDR speed table 2011-10-09 17:57:53 -05:00
eth_hydra.c fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers 2011-10-18 00:36:55 -05:00
eth_p4080.c powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) 2011-10-20 16:01:37 -05:00
p3041ds_ddr.c powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) 2011-04-27 22:29:04 -05:00
p4080ds_ddr.c powerpc/85xx: Update fixed DDR3 timing table for P4080DS 2011-04-04 09:24:41 -05:00
p5020ds_ddr.c powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) 2011-04-27 22:29:04 -05:00