776 lines
18 KiB
ArmAsm
776 lines
18 KiB
ArmAsm
/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* U-Boot - Startup Code for MPC8220 CPUs
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*/
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#include <config.h>
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#include <mpc8220.h>
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#include <version.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#endif
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/* We don't want the MMU yet.
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*/
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#undef MSR_KERNEL
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/* Floating Point enable, Machine Check and Recoverable Interr. */
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#ifdef DEBUG
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#define MSR_KERNEL (MSR_FP|MSR_RI)
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#else
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#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
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#endif
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r14 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* Version string
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*/
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.data
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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/*
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* Exception vectors
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*/
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.text
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. = EXC_OFF_SYS_RESET
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.globl _start
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_start:
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li r21, BOOTFLAG_COLD /* Normal Power-On */
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nop
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b boot_cold
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. = EXC_OFF_SYS_RESET + 0x10
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.globl _start_warm
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_start_warm:
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li r21, BOOTFLAG_WARM /* Software reboot */
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b boot_warm
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boot_cold:
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boot_warm:
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mfmsr r5 /* save msr contents */
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/* replace default MBAR base address from 0x80000000
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to 0xf0000000 */
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#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
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lis r3, CFG_MBAR@h
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ori r3, r3, CFG_MBAR@l
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/* MBAR is mirrored into the MBAR SPR */
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mtspr MBAR,r3
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mtspr SPRN_SPRG7W,r3
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lis r4, CFG_DEFAULT_MBAR@h
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stw r3, 0(r4)
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#endif /* CFG_DEFAULT_MBAR */
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/* Initialise the MPC8220 processor core */
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/*--------------------------------------------------------------*/
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bl init_8220_core
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/* initialize some things that are hard to access from C */
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/*--------------------------------------------------------------*/
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/* set up stack in on-chip SRAM */
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lis r3, CFG_INIT_RAM_ADDR@h
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ori r3, r3, CFG_INIT_RAM_ADDR@l
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ori r1, r3, CFG_INIT_SP_OFFSET
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/* let the C-code set up the rest */
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/* */
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/* Be careful to keep code relocatable ! */
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/*--------------------------------------------------------------*/
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GET_GOT /* initialize GOT access */
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/* r3: IMMR */
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bl cpu_init_f /* run low-level CPU init code (in Flash)*/
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mr r3, r21
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/* r3: BOOTFLAG */
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bl board_init_f /* run 1st part of board init code (in Flash)*/
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/*
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* Vector Table
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*/
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.globl _start_of_vectors
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_start_of_vectors:
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/* Machine check */
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STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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*/
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
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STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
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STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
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#ifdef DEBUG
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. = 0x1300
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/*
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* This exception occurs when the program counter matches the
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* Instruction Address Breakpoint Register (IABR).
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*
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* I want the cpu to halt if this occurs so I can hunt around
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* with the debugger and look at things.
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*
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* When DEBUG is defined, both machine check enable (in the MSR)
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* and checkstop reset enable (in the reset mode register) are
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* turned off and so a checkstop condition will result in the cpu
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* halting.
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*
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* I force the cpu into a checkstop condition by putting an illegal
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* instruction here (at least this is the theory).
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*
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* well - that didnt work, so just do an infinite loop!
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*/
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1: b 1b
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#else
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STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
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#endif
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STD_EXCEPTION(0x1400, SMI, UnknownException)
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STD_EXCEPTION(0x1500, Trap_15, UnknownException)
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STD_EXCEPTION(0x1600, Trap_16, UnknownException)
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STD_EXCEPTION(0x1700, Trap_17, UnknownException)
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STD_EXCEPTION(0x1800, Trap_18, UnknownException)
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STD_EXCEPTION(0x1900, Trap_19, UnknownException)
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STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
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STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
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STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
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STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
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STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
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STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
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STD_EXCEPTION(0x2000, Trap_20, UnknownException)
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STD_EXCEPTION(0x2100, Trap_21, UnknownException)
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STD_EXCEPTION(0x2200, Trap_22, UnknownException)
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STD_EXCEPTION(0x2300, Trap_23, UnknownException)
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STD_EXCEPTION(0x2400, Trap_24, UnknownException)
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STD_EXCEPTION(0x2500, Trap_25, UnknownException)
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STD_EXCEPTION(0x2600, Trap_26, UnknownException)
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STD_EXCEPTION(0x2700, Trap_27, UnknownException)
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STD_EXCEPTION(0x2800, Trap_28, UnknownException)
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STD_EXCEPTION(0x2900, Trap_29, UnknownException)
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STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
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STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
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STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
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STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
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STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
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STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x3000
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/*
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* This code finishes saving the registers to the exception frame
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* and jumps to the appropriate handler for the exception.
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* Register r21 is pointer into trap frame, r1 has new stack pointer.
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*/
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.globl transfer_to_handler
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transfer_to_handler:
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stw r22,_NIP(r21)
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lis r22,MSR_POW@h
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andc r23,r23,r22
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stw r23,_MSR(r21)
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SAVE_GPR(7, r21)
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SAVE_4GPRS(8, r21)
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SAVE_8GPRS(12, r21)
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SAVE_8GPRS(24, r21)
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mflr r23
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andi. r24,r23,0x3f00 /* get vector offset */
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stw r24,TRAP(r21)
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li r22,0
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stw r22,RESULT(r21)
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lwz r24,0(r23) /* virtual address of handler */
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lwz r23,4(r23) /* where to go when done */
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mtspr SRR0,r24
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mtspr SRR1,r20
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mtlr r23
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SYNC
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rfi /* jump to handler, enable MMU */
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int_return:
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mfmsr r28 /* Disable interrupts */
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li r4,0
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ori r4,r4,MSR_EE
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andc r28,r28,r4
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SYNC /* Some chip revs need this... */
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mtmsr r28
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SYNC
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lwz r2,_CTR(r1)
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lwz r0,_LINK(r1)
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mtctr r2
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mtlr r0
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lwz r2,_XER(r1)
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lwz r0,_CCR(r1)
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mtspr XER,r2
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mtcrf 0xFF,r0
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REST_10GPRS(3, r1)
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REST_10GPRS(13, r1)
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REST_8GPRS(23, r1)
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REST_GPR(31, r1)
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lwz r2,_NIP(r1) /* Restore environment */
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lwz r0,_MSR(r1)
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mtspr SRR0,r2
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mtspr SRR1,r0
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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SYNC
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rfi
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/*
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* This code initialises the MPC8220 processor core
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* (conforms to PowerPC 603e spec)
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* Note: expects original MSR contents to be in r5.
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*/
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.globl init_8220_core
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init_8220_core:
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/* Initialize machine status; enable machine check interrupt */
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/*--------------------------------------------------------------*/
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li r3, MSR_KERNEL /* Set ME and RI flags */
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rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
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#ifdef DEBUG
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rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
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#endif
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SYNC /* Some chip revs need this... */
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mtmsr r3
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SYNC
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mtspr SRR1, r3 /* Make SRR1 match MSR */
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/* Initialize the Hardware Implementation-dependent Registers */
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/* HID0 also contains cache control */
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/*--------------------------------------------------------------*/
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lis r3, CFG_HID0_INIT@h
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ori r3, r3, CFG_HID0_INIT@l
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SYNC
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mtspr HID0, r3
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lis r3, CFG_HID0_FINAL@h
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ori r3, r3, CFG_HID0_FINAL@l
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SYNC
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mtspr HID0, r3
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/* Enable Extra BATs */
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mfspr r3, 1011 /* HID2 */
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lis r4, 0x0004
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ori r4, r4, 0x0000
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or r4, r4, r3
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mtspr 1011, r4
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sync
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/* clear all BAT's */
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/*--------------------------------------------------------------*/
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li r0, 0
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mtspr DBAT0U, r0
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mtspr DBAT0L, r0
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mtspr DBAT1U, r0
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mtspr DBAT1L, r0
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mtspr DBAT2U, r0
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mtspr DBAT2L, r0
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mtspr DBAT3U, r0
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mtspr DBAT3L, r0
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mtspr DBAT4U, r0
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mtspr DBAT4L, r0
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mtspr DBAT5U, r0
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mtspr DBAT5L, r0
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mtspr DBAT6U, r0
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mtspr DBAT6L, r0
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mtspr DBAT7U, r0
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mtspr DBAT7L, r0
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mtspr IBAT0U, r0
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mtspr IBAT0L, r0
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mtspr IBAT1U, r0
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mtspr IBAT1L, r0
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mtspr IBAT2U, r0
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mtspr IBAT2L, r0
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mtspr IBAT3U, r0
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mtspr IBAT3L, r0
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mtspr IBAT4U, r0
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mtspr IBAT4L, r0
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mtspr IBAT5U, r0
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mtspr IBAT5L, r0
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mtspr IBAT6U, r0
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mtspr IBAT6L, r0
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mtspr IBAT7U, r0
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mtspr IBAT7L, r0
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SYNC
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/* invalidate all tlb's */
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/* */
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/* From the 603e User Manual: "The 603e provides the ability to */
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/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
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/* instruction invalidates the TLB entry indexed by the EA, and */
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/* operates on both the instruction and data TLBs simultaneously*/
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/* invalidating four TLB entries (both sets in each TLB). The */
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/* index corresponds to bits 15-19 of the EA. To invalidate all */
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/* entries within both TLBs, 32 tlbie instructions should be */
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/* issued, incrementing this field by one each time." */
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/* */
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/* "Note that the tlbia instruction is not implemented on the */
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/* 603e." */
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/* */
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/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
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/* incrementing by 0x1000 each time. The code below is sort of */
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/* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
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/* */
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/*--------------------------------------------------------------*/
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li r3, 32
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mtctr r3
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li r3, 0
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1: tlbie r3
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addi r3, r3, 0x1000
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bdnz 1b
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SYNC
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/* Done! */
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/*--------------------------------------------------------------*/
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blr
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/* Cache functions.
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*
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* Note: requires that all cache bits in
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* HID0 are in the low half word.
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*/
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.globl icache_enable
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icache_enable:
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lis r4, 0
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ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */
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rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
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/*
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* The setting of the instruction cache enable (ICE) bit must be
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* preceded by an isync instruction to prevent the cache from being
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* enabled or disabled while an instruction access is in progress.
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*/
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isync
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mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
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mtspr HID0, r3 /* using 2 consec instructions */
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isync
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blr
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.globl icache_disable
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icache_disable:
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mfspr r3, HID0
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rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */
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mtspr HID0, r3
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isync
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blr
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.globl icache_status
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icache_status:
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mfspr r3, HID0
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rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
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blr
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.globl dcache_enable
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dcache_enable:
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lis r4, 0
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ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */
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rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */
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/* Enable address translation in MSR bit */
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mfmsr r5
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ori r5, r5, 0x
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/*
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* The setting of the instruction cache enable (ICE) bit must be
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* preceded by an isync instruction to prevent the cache from being
|
|
* enabled or disabled while an instruction access is in progress.
|
|
*/
|
|
isync
|
|
mtspr HID0, r4 /* Enable Data Cache & Inval cache*/
|
|
mtspr HID0, r3 /* using 2 consec instructions */
|
|
isync
|
|
blr
|
|
|
|
.globl dcache_disable
|
|
dcache_disable:
|
|
mfspr r3, HID0
|
|
rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */
|
|
mtspr HID0, r3
|
|
isync
|
|
blr
|
|
|
|
.globl dcache_status
|
|
dcache_status:
|
|
mfspr r3, HID0
|
|
rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
|
|
blr
|
|
|
|
.globl get_pvr
|
|
get_pvr:
|
|
mfspr r3, PVR
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* void relocate_code (addr_sp, gd, addr_moni)
|
|
*
|
|
* This "function" does not return, instead it continues in RAM
|
|
* after relocating the monitor code.
|
|
*
|
|
* r3 = dest
|
|
* r4 = src
|
|
* r5 = length in bytes
|
|
* r6 = cachelinesize
|
|
*/
|
|
.globl relocate_code
|
|
relocate_code:
|
|
mr r1, r3 /* Set new stack pointer */
|
|
mr r9, r4 /* Save copy of Global Data pointer */
|
|
mr r10, r5 /* Save copy of Destination Address */
|
|
|
|
mr r3, r5 /* Destination Address */
|
|
lis r4, CFG_MONITOR_BASE@h /* Source Address */
|
|
ori r4, r4, CFG_MONITOR_BASE@l
|
|
lwz r5, GOT(__init_end)
|
|
sub r5, r5, r4
|
|
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
|
|
|
|
/*
|
|
* Fix GOT pointer:
|
|
*
|
|
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
|
|
*
|
|
* Offset:
|
|
*/
|
|
sub r15, r10, r4
|
|
|
|
/* First our own GOT */
|
|
add r14, r14, r15
|
|
/* then the one used by the C code */
|
|
add r30, r30, r15
|
|
|
|
/*
|
|
* Now relocate code
|
|
*/
|
|
|
|
cmplw cr1,r3,r4
|
|
addi r0,r5,3
|
|
srwi. r0,r0,2
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
beq 7f /* Protect against 0 count */
|
|
mtctr r0
|
|
bge cr1,2f
|
|
|
|
la r8,-4(r4)
|
|
la r7,-4(r3)
|
|
1: lwzu r0,4(r8)
|
|
stwu r0,4(r7)
|
|
bdnz 1b
|
|
b 4f
|
|
|
|
2: slwi r0,r0,2
|
|
add r8,r4,r0
|
|
add r7,r3,r0
|
|
3: lwzu r0,-4(r8)
|
|
stwu r0,-4(r7)
|
|
bdnz 3b
|
|
|
|
/*
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
* address. Otherwise we might miss one cache line.
|
|
*/
|
|
4: cmpwi r6,0
|
|
add r5,r3,r5
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
subi r0,r6,1
|
|
andc r3,r3,r0
|
|
mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
|
|
rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
|
|
cmpwi r7,0
|
|
beq 9f
|
|
mr r4,r3
|
|
5: dcbst 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 5b
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
|
|
rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
|
|
cmpwi r7,0
|
|
beq 7f
|
|
mr r4,r3
|
|
6: icbi 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 6b
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
|
|
/*
|
|
* We are done. Do not return, instead branch to second part of board
|
|
* initialization, now running from RAM.
|
|
*/
|
|
|
|
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
mtlr r0
|
|
blr
|
|
|
|
in_ram:
|
|
|
|
/*
|
|
* Relocation Function, r14 point to got2+0x8000
|
|
*
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
* already puts a few entries in the table.
|
|
*/
|
|
li r0,__got2_entries@sectoff@l
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
mtctr r0
|
|
sub r11,r3,r11
|
|
addi r3,r3,-4
|
|
1: lwzu r0,4(r3)
|
|
add r0,r0,r11
|
|
stw r0,0(r3)
|
|
bdnz 1b
|
|
|
|
/*
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
* in case we need to move ourselves again.
|
|
*/
|
|
2: li r0,__fixup_entries@sectoff@l
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
cmpwi r0,0
|
|
mtctr r0
|
|
addi r3,r3,-4
|
|
beq 4f
|
|
3: lwzu r4,4(r3)
|
|
lwzux r0,r4,r11
|
|
add r0,r0,r11
|
|
stw r10,0(r3)
|
|
stw r0,0(r4)
|
|
bdnz 3b
|
|
4:
|
|
clear_bss:
|
|
/*
|
|
* Now clear BSS segment
|
|
*/
|
|
lwz r3,GOT(__bss_start)
|
|
lwz r4,GOT(_end)
|
|
|
|
cmplw 0, r3, r4
|
|
beq 6f
|
|
|
|
li r0, 0
|
|
5:
|
|
stw r0, 0(r3)
|
|
addi r3, r3, 4
|
|
cmplw 0, r3, r4
|
|
bne 5b
|
|
6:
|
|
|
|
mr r3, r9 /* Global Data pointer */
|
|
mr r4, r10 /* Destination Address */
|
|
bl board_init_r
|
|
|
|
/*
|
|
* Copy exception vector code to low memory
|
|
*
|
|
* r3: dest_addr
|
|
* r7: source address, r8: end address, r9: target address
|
|
*/
|
|
.globl trap_init
|
|
trap_init:
|
|
lwz r7, GOT(_start)
|
|
lwz r8, GOT(_end_of_vectors)
|
|
|
|
li r9, 0x100 /* reset vector always at 0x100 */
|
|
|
|
cmplw 0, r7, r8
|
|
bgelr /* return if r7>=r8 - just in case */
|
|
|
|
mflr r4 /* save link register */
|
|
1:
|
|
lwz r0, 0(r7)
|
|
stw r0, 0(r9)
|
|
addi r7, r7, 4
|
|
addi r9, r9, 4
|
|
cmplw 0, r7, r8
|
|
bne 1b
|
|
|
|
/*
|
|
* relocate `hdlr' and `int_return' entries
|
|
*/
|
|
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
|
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
|
2:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 2b
|
|
|
|
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
|
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
|
3:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 3b
|
|
|
|
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
|
|
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
4:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 4b
|
|
|
|
mfmsr r3 /* now that the vectors have */
|
|
lis r7, MSR_IP@h /* relocated into low memory */
|
|
ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
|
|
andc r3, r3, r7 /* (if it was on) */
|
|
SYNC /* Some chip revs need this... */
|
|
mtmsr r3
|
|
SYNC
|
|
|
|
mtlr r4 /* restore link register */
|
|
blr
|
|
|
|
/*
|
|
* Function: relocate entries for one exception vector
|
|
*/
|
|
trap_reloc:
|
|
lwz r0, 0(r7) /* hdlr ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 0(r7)
|
|
|
|
lwz r0, 4(r7) /* int_return ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 4(r7)
|
|
|
|
blr
|