692 lines
16 KiB
C
692 lines
16 KiB
C
/*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code for the MPC83xx family.
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*
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* Derived from the MPC8260 and MPC85xx.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc83xx.h>
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#include <asm/processor.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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#elif defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <libfdt_env.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int checkcpu(void)
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{
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volatile immap_t *immr;
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ulong clock = gd->cpu_clk;
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u32 pvr = get_pvr();
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u32 spridr;
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char buf[32];
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immr = (immap_t *)CFG_IMMR;
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puts("CPU: ");
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switch (pvr & 0xffff0000) {
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case PVR_E300C1:
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printf("e300c1, ");
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break;
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case PVR_E300C2:
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printf("e300c2, ");
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break;
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case PVR_E300C3:
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printf("e300c3, ");
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break;
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default:
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printf("Unknown core, ");
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}
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spridr = immr->sysconf.spridr;
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switch(spridr) {
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case SPR_8349E_REV10:
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case SPR_8349E_REV11:
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case SPR_8349E_REV31:
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puts("MPC8349E, ");
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break;
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case SPR_8349_REV10:
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case SPR_8349_REV11:
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case SPR_8349_REV31:
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puts("MPC8349, ");
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break;
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case SPR_8347E_REV10_TBGA:
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case SPR_8347E_REV11_TBGA:
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case SPR_8347E_REV31_TBGA:
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case SPR_8347E_REV10_PBGA:
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case SPR_8347E_REV11_PBGA:
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case SPR_8347E_REV31_PBGA:
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puts("MPC8347E, ");
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break;
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case SPR_8347_REV10_TBGA:
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case SPR_8347_REV11_TBGA:
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case SPR_8347_REV31_TBGA:
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case SPR_8347_REV10_PBGA:
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case SPR_8347_REV11_PBGA:
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case SPR_8347_REV31_PBGA:
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puts("MPC8347, ");
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break;
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case SPR_8343E_REV10:
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case SPR_8343E_REV11:
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case SPR_8343E_REV31:
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puts("MPC8343E, ");
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break;
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case SPR_8343_REV10:
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case SPR_8343_REV11:
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case SPR_8343_REV31:
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puts("MPC8343, ");
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break;
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case SPR_8360E_REV10:
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case SPR_8360E_REV11:
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case SPR_8360E_REV12:
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case SPR_8360E_REV20:
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case SPR_8360E_REV21:
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puts("MPC8360E, ");
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break;
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case SPR_8360_REV10:
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case SPR_8360_REV11:
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case SPR_8360_REV12:
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case SPR_8360_REV20:
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case SPR_8360_REV21:
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puts("MPC8360, ");
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break;
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case SPR_8323E_REV10:
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case SPR_8323E_REV11:
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puts("MPC8323E, ");
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break;
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case SPR_8323_REV10:
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case SPR_8323_REV11:
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puts("MPC8323, ");
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break;
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case SPR_8321E_REV10:
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case SPR_8321E_REV11:
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puts("MPC8321E, ");
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break;
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case SPR_8321_REV10:
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case SPR_8321_REV11:
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puts("MPC8321, ");
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break;
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case SPR_8311_REV10:
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puts("MPC8311, ");
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break;
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case SPR_8311E_REV10:
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puts("MPC8311E, ");
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break;
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case SPR_8313_REV10:
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puts("MPC8313, ");
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break;
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case SPR_8313E_REV10:
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puts("MPC8313E, ");
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break;
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default:
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printf("Rev: Unknown revision number:%08x\n"
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"Warning: Unsupported cpu revision!\n",spridr);
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return 0;
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}
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#if defined(CONFIG_MPC834X)
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/* Multiple revisons of 834x processors may have the same SPRIDR value.
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* So use PVR to identify the revision number.
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*/
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printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
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#else
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printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
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#endif
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printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
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return 0;
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}
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/*
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* Program a UPM with the code supplied in the table.
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*
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* The 'dummy' variable is used to increment the MAD. 'dummy' is
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* supposed to be a pointer to the memory of the device being
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* programmed by the UPM. The data in the MDR is written into
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* memory and the MAD is incremented every time there's a read
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* from 'dummy'. Unfortunately, the current prototype for this
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* function doesn't allow for passing the address of this
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* device, and changing the prototype will break a number lots
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* of other code, so we need to use a round-about way of finding
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* the value for 'dummy'.
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*
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* The value can be extracted from the base address bits of the
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* Base Register (BR) associated with the specific UPM. To find
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* that BR, we need to scan all 8 BRs until we find the one that
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* has its MSEL bits matching the UPM we want. Once we know the
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* right BR, we can extract the base address bits from it.
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*
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* The MxMR and the BR and OR of the chosen bank should all be
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* configured before calling this function.
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*
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* Parameters:
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* upm: 0=UPMA, 1=UPMB, 2=UPMC
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* table: Pointer to an array of values to program
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* size: Number of elements in the array. Must be 64 or less.
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*/
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void upmconfig (uint upm, uint *table, uint size)
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{
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#if defined(CONFIG_MPC834X)
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile lbus83xx_t *lbus = &immap->lbus;
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volatile uchar *dummy = NULL;
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const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
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volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
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uint i;
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/* Scan all the banks to determine the base address of the device */
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for (i = 0; i < 8; i++) {
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if ((lbus->bank[i].br & BR_MSEL) == msel) {
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dummy = (uchar *) (lbus->bank[i].br & BR_BA);
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break;
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}
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}
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if (!dummy) {
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printf("Error: %s() could not find matching BR\n", __FUNCTION__);
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hang();
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}
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/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
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*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
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for (i = 0; i < size; i++) {
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lbus->mdr = table[i];
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__asm__ __volatile__ ("sync");
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*dummy; /* Write the value to memory and increment MAD */
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__asm__ __volatile__ ("sync");
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}
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/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
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*mxmr &= 0xCFFFFFC0;
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#else
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printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
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hang();
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#endif
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}
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int
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do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong msr;
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#ifndef MPC83xx_RESET
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ulong addr;
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#endif
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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#ifdef MPC83xx_RESET
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~( MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/* enable Reset Control Reg */
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immap->reset.rpr = 0x52535445;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* confirm Reset Control Reg is enabled */
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while(!((immap->reset.rcer) & RCER_CRE));
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printf("Resetting the board.");
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printf("\n");
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udelay(200);
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/* perform reset, only one bit */
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immap->reset.rcr = RCR_SWHR;
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#else /* ! MPC83xx_RESET */
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immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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addr = CFG_RESET_ADDRESS;
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printf("resetting the board.");
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printf("\n");
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((void (*)(void)) addr) ();
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#endif /* MPC83xx_RESET */
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return 1;
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}
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*/
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unsigned long get_tbclk(void)
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{
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ulong tbclk;
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tbclk = (gd->bus_clk + 3L) / 4L;
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return tbclk;
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}
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset (void)
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{
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int re_enable = disable_interrupts();
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/* Reset the 83xx watchdog */
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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immr->wdt.swsrr = 0x556c;
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immr->wdt.swsrr = 0xaa39;
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if (re_enable)
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enable_interrupts ();
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT)
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/*
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* "Setter" functions used to add/modify FDT entries.
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*/
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static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
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{
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/*
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* Fix it up if it exists, don't create it if it doesn't exist.
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*/
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if (fdt_get_property(blob, nodeoffset, name, 0)) {
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return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
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}
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return 0;
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}
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#ifdef CONFIG_HAS_ETH1
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/* second onboard ethernet port */
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static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
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{
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/*
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* Fix it up if it exists, don't create it if it doesn't exist.
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*/
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if (fdt_get_property(blob, nodeoffset, name, 0)) {
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return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_HAS_ETH2
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/* third onboard ethernet port */
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static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
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{
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/*
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* Fix it up if it exists, don't create it if it doesn't exist.
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*/
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if (fdt_get_property(blob, nodeoffset, name, 0)) {
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return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_HAS_ETH3
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/* fourth onboard ethernet port */
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static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
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{
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/*
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* Fix it up if it exists, don't create it if it doesn't exist.
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*/
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if (fdt_get_property(blob, nodeoffset, name, 0)) {
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return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
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}
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return 0;
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}
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#endif
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static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
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{
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u32 tmp;
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/*
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* Create or update the property.
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*/
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tmp = cpu_to_be32(bd->bi_busfreq);
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return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
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}
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static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
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{
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u32 tmp;
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/*
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* Create or update the property.
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*/
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tmp = cpu_to_be32(OF_TBCLK);
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return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
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}
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/*
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* Fixups to the fdt.
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*/
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static const struct {
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char *node;
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char *prop;
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int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
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} fixup_props[] = {
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{ "/cpus/" OF_CPU,
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"timebase-frequency",
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fdt_set_tbfreq
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},
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{ "/cpus/" OF_CPU,
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"bus-frequency",
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fdt_set_busfreq
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},
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{ "/cpus/" OF_CPU,
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"clock-frequency",
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fdt_set_busfreq
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},
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{ "/" OF_SOC "/serial@4500",
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"clock-frequency",
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fdt_set_busfreq
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},
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{ "/" OF_SOC "/serial@4600",
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"clock-frequency",
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fdt_set_busfreq
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},
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#ifdef CONFIG_TSEC1
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{ "/" OF_SOC "/ethernet@24000",
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"mac-address",
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fdt_set_eth0
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},
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{ "/" OF_SOC "/ethernet@24000",
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"local-mac-address",
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fdt_set_eth0
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},
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#endif
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#ifdef CONFIG_TSEC2
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{ "/" OF_SOC "/ethernet@25000",
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"mac-address",
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fdt_set_eth1
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},
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{ "/" OF_SOC "/ethernet@25000",
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"local-mac-address",
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fdt_set_eth1
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},
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#endif
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#ifdef CONFIG_UEC_ETH1
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#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
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{ "/" OF_QE "/ucc@2000",
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"mac-address",
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fdt_set_eth0
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},
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{ "/" OF_QE "/ucc@2000",
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"local-mac-address",
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fdt_set_eth0
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},
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#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
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{ "/" OF_QE "/ucc@2200",
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"mac-address",
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fdt_set_eth0
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},
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{ "/" OF_QE "/ucc@2200",
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"local-mac-address",
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fdt_set_eth0
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},
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#endif
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#endif /* CONFIG_UEC_ETH1 */
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#ifdef CONFIG_UEC_ETH2
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#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
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{ "/" OF_QE "/ucc@3000",
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"mac-address",
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fdt_set_eth1
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},
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{ "/" OF_QE "/ucc@3000",
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"local-mac-address",
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fdt_set_eth1
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},
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#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
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{ "/" OF_QE "/ucc@3200",
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"mac-address",
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fdt_set_eth1
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},
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{ "/" OF_QE "/ucc@3200",
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"local-mac-address",
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fdt_set_eth1
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},
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#endif
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#endif /* CONFIG_UEC_ETH2 */
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};
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void
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ft_cpu_setup(void *blob, bd_t *bd)
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{
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int nodeoffset;
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int err;
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int j;
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for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
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nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node);
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if (nodeoffset >= 0) {
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err = fixup_props[j].set_fn(blob, nodeoffset,
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fixup_props[j].prop, bd);
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if (err < 0)
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debug("Problem setting %s = %s: %s\n",
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fixup_props[j].node,
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fixup_props[j].prop,
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fdt_strerror(err));
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} else {
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debug("Couldn't find %s: %s\n",
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fixup_props[j].node,
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fdt_strerror(nodeoffset));
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}
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}
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}
|
|
#elif defined(CONFIG_OF_FLAT_TREE)
|
|
void
|
|
ft_cpu_setup(void *blob, bd_t *bd)
|
|
{
|
|
u32 *p;
|
|
int len;
|
|
ulong clock;
|
|
|
|
clock = bd->bi_busfreq;
|
|
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
|
|
if (p != NULL)
|
|
*p = cpu_to_be32(clock);
|
|
|
|
#ifdef CONFIG_TSEC1
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
#endif
|
|
|
|
#ifdef CONFIG_TSEC2
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
|
|
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
#endif
|
|
|
|
#ifdef CONFIG_UEC_ETH1
|
|
#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enetaddr, 6);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_UEC_ETH2
|
|
#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
|
|
p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
|
|
if (p != NULL)
|
|
memcpy(p, bd->bi_enet1addr, 6);
|
|
#endif
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_DDR_ECC)
|
|
void dma_init(void)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile dma83xx_t *dma = &immap->dma;
|
|
volatile u32 status = swab32(dma->dmasr0);
|
|
volatile u32 dmamr0 = swab32(dma->dmamr0);
|
|
|
|
debug("DMA-init\n");
|
|
|
|
/* initialize DMASARn, DMADAR and DMAABCRn */
|
|
dma->dmadar0 = (u32)0;
|
|
dma->dmasar0 = (u32)0;
|
|
dma->dmabcr0 = 0;
|
|
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* clear CS bit */
|
|
dmamr0 &= ~DMA_CHANNEL_START;
|
|
dma->dmamr0 = swab32(dmamr0);
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* while the channel is busy, spin */
|
|
while(status & DMA_CHANNEL_BUSY) {
|
|
status = swab32(dma->dmasr0);
|
|
}
|
|
|
|
debug("DMA-init end\n");
|
|
}
|
|
|
|
uint dma_check(void)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile dma83xx_t *dma = &immap->dma;
|
|
volatile u32 status = swab32(dma->dmasr0);
|
|
volatile u32 byte_count = swab32(dma->dmabcr0);
|
|
|
|
/* while the channel is busy, spin */
|
|
while (status & DMA_CHANNEL_BUSY) {
|
|
status = swab32(dma->dmasr0);
|
|
}
|
|
|
|
if (status & DMA_CHANNEL_TRANSFER_ERROR) {
|
|
printf ("DMA Error: status = %x @ %d\n", status, byte_count);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
int dma_xfer(void *dest, u32 count, void *src)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile dma83xx_t *dma = &immap->dma;
|
|
volatile u32 dmamr0;
|
|
|
|
/* initialize DMASARn, DMADAR and DMAABCRn */
|
|
dma->dmadar0 = swab32((u32)dest);
|
|
dma->dmasar0 = swab32((u32)src);
|
|
dma->dmabcr0 = swab32(count);
|
|
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* init direct transfer, clear CS bit */
|
|
dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
|
|
DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
|
|
DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
|
|
|
|
dma->dmamr0 = swab32(dmamr0);
|
|
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* set CS to start DMA transfer */
|
|
dmamr0 |= DMA_CHANNEL_START;
|
|
dma->dmamr0 = swab32(dmamr0);
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
return ((int)dma_check());
|
|
}
|
|
#endif /*CONFIG_DDR_ECC*/
|