100 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
			
		
		
	
	
			100 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
| 
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| 
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| 	U-Boot for Wind River SBC834x Boards
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| 	====================================
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| 
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| 
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| The Wind River SBC834x board is a 6U form factor (not CPCI) reference
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| design that uses the MPC8347E or MPC8349E processor.  U-Boot support
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| for this board is heavily based on the existing U-Boot support for
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| Freescale MPC8349 reference boards.
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| 
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| Support has been primarily tested on the SBC8349 version of the board,
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| although earlier versions were also tested on the SBC8347.  The primary
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| difference in the two is the level of PCI functionality.
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| 
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| 	http://www.windriver.com/products/OCD/SBC8347E_49E/
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| 
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| 
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| Flash Details:
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| ==============
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| 
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| The flash type is intel 28F640Jx (4096x16) [one device].  Base address
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| is 0xFF80_0000 which is also where the Hardware Reset Configuration
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| Word (HRCW) is stored.  Caution should be used to not overwrite the
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| HRCW, or "CF RCW" with a Wind River ICE will be required to restore
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| the HRCW and allow the board to enter background mode for further
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| steps in the flash process.
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| 
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| 
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| Restoring a corrupted or missing flash image:
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| =============================================
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| 
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| Details for storing U-boot to flash using a Wind River ICE can be found
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| on page 19 of the board manual (request ERG-00328-001).  The following
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| is a summary of that information:
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| 
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|   - Connect ICE and establish connection to it from WorkBench/OCD.
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|   - Ensure you have background mode (BKM) in the OCD terminal window.
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|   - Select the appropriate flash type (listed above)
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|   - Prepare a u-boot image by using the Wind River Convert utility;
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|     by using "Convert and Add file" on the ELF file from your build.
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|     Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are
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|     trying to preserve your old environment settings).
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|   - Set the start address of the erase/flash process to FFF0_0000
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|   - Set the target RAM required to 64kB.
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|   - Select sectors for erasing (see note on enviroment below)
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|   - Select Erase and Reprogram.
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| 
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| Note that some versions of the register files used with Workbench
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| would zero some TSEC registers, which inhibits ethernet operation
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| by u-boot when this register file is played to the target.  Using
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| "INN" in the OCD terminal window instead of "IN" before the "GO"
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| will not play the register file, and allow u-boot to use the TSEC
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| interface while executed from the ICE "GO" command.
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| 
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| Alternatively, you can locate the register file which will be named
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| WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
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| beginning with "SCGA TSEC1" and "SCGA TSEC2".  This allows you to
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| use all the remaining register file content.
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| 
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| If you wish to preserve your prior U-Boot environment settings,
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| then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF.
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| The size for converting (and erasing) must be at least as large
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| as u-boot.bin.
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| 
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| 
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| Updating U-Boot with U-Boot:
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| ============================
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| 
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| This procedure is very similar to other boards that have u-boot installed.
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| Assuming that the network has been configured, and that the new u-boot.bin
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| has been copied to the TFTP server, the commands are:
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| 
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| 	tftp 200000 u-boot.bin
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| 	protect off all
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| 	erase fff00000 fff3ffff
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| 	cp.b 200000 fff00000 3ffff
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| 	protect on all
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| 
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| 
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| PCI:
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| ====
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| 
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| This board and U-Boot have been tested with PCI built in, on a SBC8349
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| and confirmed that the "pci" command showed the intel e1000 that was
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| present in the PCI slot.  Note that if a 33MHz 32bit card is inserted
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| in the slot, then the whole board will clock down to a 33MHz base
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| clock instead of the default 66MHz.  This will change the baud clocks
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| and mess up your serial console output.  If you want to use a 33MHz PCI
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| card, then you should build a U-Boot with #undef PCI_66M in the
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| include/configs/sbc8349.h and store this to flash prior to powering down
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| the board and inserting the 33MHz PCI card.
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| 
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| By default PCI support is disabled to better support very early
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| revision MPC834x chips with possible PCI issues.  Also PCI support is
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| untested on the sbc8347 variants at this point in time.
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| 
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| 
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| 						Paul Gortmaker, 01/2007
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