455 lines
13 KiB
C
455 lines
13 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995 Waldorf GmbH
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* Copyright (C) 1994 - 2000 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2000 FSMLabs, Inc.
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#include <linux/config.h>
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#if 0
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#include <linux/pagemap.h>
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#endif
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* Sane hardware offers swapping of I/O space accesses in hardware; less
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* sane hardware forces software to fiddle with this ...
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*/
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#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
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#define __ioswab8(x) (x)
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#define __ioswab16(x) swab16(x)
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#define __ioswab32(x) swab32(x)
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#else
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#define __ioswab8(x) (x)
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#define __ioswab16(x) (x)
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#define __ioswab32(x) (x)
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#endif
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/*
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* This file contains the definitions for the MIPS counterpart of the
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* x86 in/out instructions. This heap of macros and C results in much
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* better code than the approach of doing it in plain C. The macros
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* result in code that is to fast for certain hardware. On the other
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* side the performance of the string functions should be improved for
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* sake of certain devices like EIDE disks that do highspeed polled I/O.
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*
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* Ralf
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*
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* This file contains the definitions for the x86 IO instructions
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* inb/inw/inl/outb/outw/outl and the "string versions" of the same
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* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
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* versions of the single-IO instructions (inb_p/inw_p/..).
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*
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* This file is not meant to be obfuscating: it's just complicated
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* to (a) handle it all in a way that makes gcc able to optimize it
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* as well as possible and (b) trying to avoid writing the same thing
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* over and over again with slight variations and possibly making a
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* mistake somewhere.
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*/
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/*
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* On MIPS I/O ports are memory mapped, so we access them using normal
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* load/store instructions. mips_io_port_base is the virtual address to
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* which all ports are being mapped. For sake of efficiency some code
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* assumes that this is an address that can be loaded with a single lui
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* instruction, so the lower 16 bits must be zero. Should be true on
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* on any sane architecture; generic code does not use this assumption.
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*/
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extern unsigned long mips_io_port_base;
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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* to guarantee better timings even on fast machines.
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*
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* On the other hand, I'd like to be sure of a non-existent port:
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* I feel a bit unsafe about using 0x80 (should be safe, though)
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*
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* Linus
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*
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*/
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#define __SLOW_DOWN_IO \
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__asm__ __volatile__( \
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"sb\t$0,0x80(%0)" \
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: : "r" (mips_io_port_base));
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#ifdef CONF_SLOWDOWN_IO
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#ifdef REALLY_SLOW_IO
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#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
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#else
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#define SLOW_DOWN_IO __SLOW_DOWN_IO
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#endif
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#else
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#define SLOW_DOWN_IO
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#endif
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/*
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* Change virtual addresses to physical addresses and vv.
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* These are trivial on the 1:1 Linux/MIPS mapping
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*/
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extern inline unsigned long virt_to_phys(volatile void * address)
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{
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return PHYSADDR(address);
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}
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extern inline void * phys_to_virt(unsigned long address)
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{
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return (void *)KSEG0ADDR(address);
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}
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/*
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* IO bus memory addresses are also 1:1 with the physical address
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*/
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extern inline unsigned long virt_to_bus(volatile void * address)
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{
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return PHYSADDR(address);
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}
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extern inline void * bus_to_virt(unsigned long address)
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{
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return (void *)KSEG0ADDR(address);
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}
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/*
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* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
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* for the processor.
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*/
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extern unsigned long isa_slot_offset;
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extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
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#if 0
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extern inline void *ioremap(unsigned long offset, unsigned long size)
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{
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return __ioremap(offset, size, _CACHE_UNCACHED);
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}
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extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
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{
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return __ioremap(offset, size, _CACHE_UNCACHED);
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}
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extern void iounmap(void *addr);
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#endif
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/*
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* XXX We need system specific versions of these to handle EISA address bits
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* 24-31 on SNI.
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* XXX more SNI hacks.
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*/
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#define readb(addr) (*(volatile unsigned char *)(addr))
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#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
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#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
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#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b))
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#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b))
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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/* END SNI HACKS ... */
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/*
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* ISA space is 'always mapped' on currently supported MIPS systems, no need
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* to explicitly ioremap() it. The fact that the ISA IO space is mapped
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* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
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* are physical addresses. The following constant pointer can be
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* used as the IO-area pointer (it can be iounmapped as well, so the
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* analogy with PCI is quite large):
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*/
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#define __ISA_IO_base ((char *)(PAGE_OFFSET))
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#define isa_readb(a) readb(a)
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#define isa_readw(a) readw(a)
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#define isa_readl(a) readl(a)
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#define isa_writeb(b,a) writeb(b,a)
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#define isa_writew(w,a) writew(w,a)
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#define isa_writel(l,a) writel(l,a)
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#define isa_memset_io(a,b,c) memset_io((a),(b),(c))
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#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
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#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
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/*
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* We don't have csum_partial_copy_fromio() yet, so we cheat here and
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* just copy it. The net code will then do the checksum later.
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*/
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#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
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#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
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static inline int check_signature(unsigned long io_addr,
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const unsigned char *signature, int length)
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{
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int retval = 0;
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do {
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if (readb(io_addr) != *signature)
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goto out;
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io_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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#define isa_check_signature(io, s, l) check_signature(i,s,l)
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/*
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* Talk about misusing macros..
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*/
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#define __OUT1(s) \
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extern inline void __out##s(unsigned int value, unsigned int port) {
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#define __OUT2(m) \
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__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
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#define __OUT(m,s,w) \
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__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
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__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
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__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
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SLOW_DOWN_IO; } \
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__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
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SLOW_DOWN_IO; }
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#define __IN1(t,s) \
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extern __inline__ t __in##s(unsigned int port) { t _v;
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/*
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* Required nops will be inserted by the assembler
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*/
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#define __IN2(m) \
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__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
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#define __IN(t,m,s,w) \
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__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
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__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
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__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
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__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
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#define __INS1(s) \
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extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
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#define __INS2(m) \
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if (count) \
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__asm__ __volatile__ ( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n" \
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"1:\tl" #m "\t$1,%4(%5)\n\t" \
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"subu\t%1,1\n\t" \
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"s" #m "\t$1,(%0)\n\t" \
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"bne\t$0,%1,1b\n\t" \
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"addiu\t%0,%6\n\t" \
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".set\tat\n\t" \
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".set\treorder"
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#define __INS(m,s,i) \
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__INS1(s) __INS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "i" (0), \
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"r" (mips_io_port_base+port), "I" (i) \
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: "$1");} \
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__INS1(s##c) __INS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "ir" (port), \
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"r" (mips_io_port_base), "I" (i) \
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: "$1");}
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#define __OUTS1(s) \
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extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
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#define __OUTS2(m) \
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if (count) \
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__asm__ __volatile__ ( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n" \
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"1:\tl" #m "\t$1,(%0)\n\t" \
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"subu\t%1,1\n\t" \
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"s" #m "\t$1,%4(%5)\n\t" \
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"bne\t$0,%1,1b\n\t" \
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"addiu\t%0,%6\n\t" \
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".set\tat\n\t" \
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".set\treorder"
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#define __OUTS(m,s,i) \
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__OUTS1(s) __OUTS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
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: "$1");} \
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__OUTS1(s##c) __OUTS2(m) \
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: "=r" (addr), "=r" (count) \
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: "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
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: "$1");}
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__IN(unsigned char,b,b,8)
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__IN(unsigned short,h,w,16)
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__IN(unsigned int,w,l,32)
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__OUT(b,b,8)
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__OUT(h,w,16)
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__OUT(w,l,32)
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__INS(b,b,1)
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__INS(h,w,2)
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__INS(w,l,4)
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__OUTS(b,b,1)
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__OUTS(h,w,2)
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__OUTS(w,l,4)
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/*
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* Note that due to the way __builtin_constant_p() works, you
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* - can't use it inside an inline function (it will never be true)
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* - you don't have to worry about side effects within the __builtin..
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*/
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#define outb(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outbc((val),(port)) : \
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__outb((val),(port)))
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#define inb(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inbc(port) : \
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__inb(port))
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#define outb_p(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outbc_p((val),(port)) : \
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__outb_p((val),(port)))
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#define inb_p(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inbc_p(port) : \
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__inb_p(port))
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#define outw(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outwc((val),(port)) : \
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__outw((val),(port)))
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#define inw(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inwc(port) : \
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__inw(port))
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#define outw_p(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outwc_p((val),(port)) : \
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__outw_p((val),(port)))
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#define inw_p(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inwc_p(port) : \
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__inw_p(port))
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#define outl(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outlc((val),(port)) : \
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__outl((val),(port)))
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#define inl(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inlc(port) : \
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__inl(port))
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#define outl_p(val,port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outlc_p((val),(port)) : \
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__outl_p((val),(port)))
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#define inl_p(port) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inlc_p(port) : \
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__inl_p(port))
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#define outsb(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outsbc((port),(addr),(count)) : \
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__outsb ((port),(addr),(count)))
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#define insb(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__insbc((port),(addr),(count)) : \
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__insb((port),(addr),(count)))
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#define outsw(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outswc((port),(addr),(count)) : \
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__outsw ((port),(addr),(count)))
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#define insw(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inswc((port),(addr),(count)) : \
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__insw((port),(addr),(count)))
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#define outsl(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__outslc((port),(addr),(count)) : \
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__outsl ((port),(addr),(count)))
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#define insl(port,addr,count) \
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((__builtin_constant_p((port)) && (port) < 32768) ? \
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__inslc((port),(addr),(count)) : \
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__insl((port),(addr),(count)))
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#define IO_SPACE_LIMIT 0xffff
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/*
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* The caches on some architectures aren't dma-coherent and have need to
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* handle this in software. There are three types of operations that
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* can be applied to dma buffers.
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*
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* - dma_cache_wback_inv(start, size) makes caches and coherent by
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* writing the content of the caches back to memory, if necessary.
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* The function also invalidates the affected part of the caches as
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* necessary before DMA transfers from outside to memory.
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* - dma_cache_wback(start, size) makes caches and coherent by
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* writing the content of the caches back to memory, if necessary.
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* The function also invalidates the affected part of the caches as
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* necessary before DMA transfers from outside to memory.
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* - dma_cache_inv(start, size) invalidates the affected parts of the
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* caches. Dirty lines of the caches may be written back or simply
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* be discarded. This operation is necessary before dma operations
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* to the memory.
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*/
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extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
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extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
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extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
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#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
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#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
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#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
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static inline void sync(void)
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{
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}
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#endif /* _ASM_IO_H */
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