110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*
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* Register definitions for the OMAP3 McSPI Controller
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*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _OMAP3_SPI_H_
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#define _OMAP3_SPI_H_
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#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
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#define OMAP3_MCSPI1_BASE 0x48030100
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#define OMAP3_MCSPI2_BASE 0x481A0100
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#else
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#define OMAP3_MCSPI1_BASE 0x48098000
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#define OMAP3_MCSPI2_BASE 0x4809A000
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#define OMAP3_MCSPI3_BASE 0x480B8000
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#define OMAP3_MCSPI4_BASE 0x480BA000
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#endif
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#define OMAP3_MCSPI_MAX_FREQ 48000000
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/* OMAP3 McSPI registers */
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struct mcspi_channel {
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unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
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unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
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unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
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unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
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unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
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};
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struct mcspi {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned int irqstatus; /* 0x18 */
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unsigned int irqenable; /* 0x1C */
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unsigned int wakeupenable; /* 0x20 */
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unsigned int syst; /* 0x24 */
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unsigned int modulctrl; /* 0x28 */
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struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
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/* channel1: 0x40 - 0x50, bus 0 & 1 */
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/* channel2: 0x54 - 0x64, bus 0 & 1 */
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/* channel3: 0x68 - 0x78, bus 0 */
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};
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/* per-register bitmasks */
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#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
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#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
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#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
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#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
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#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
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#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
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#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
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#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
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#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
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#define OMAP3_MCSPI_CHCONF_POL BIT(1)
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#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
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#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
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#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
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#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
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#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
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#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
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#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
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#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
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#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
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#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
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#define OMAP3_MCSPI_CHCONF_IS BIT(18)
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#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
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#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
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#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
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#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
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#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
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#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
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#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
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#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
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struct omap3_spi_slave {
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struct spi_slave slave;
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struct mcspi *regs;
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unsigned int freq;
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unsigned int mode;
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};
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static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct omap3_spi_slave, slave);
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}
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int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp,
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void *rxp, unsigned long flags);
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int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
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unsigned long flags);
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int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
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unsigned long flags);
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#endif /* _OMAP3_SPI_H_ */
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