152 lines
3.4 KiB
C
152 lines
3.4 KiB
C
/*
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* Keystone2: Architecture initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <asm/arch/msmc.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/psc_defs.h>
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#define MAX_PCI_PORTS 2
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enum pci_mode {
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ENDPOINT,
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LEGACY_ENDPOINT,
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ROOTCOMPLEX,
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};
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#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
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#define DEVCFG_MODE_SHIFT 1
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void chip_configuration_unlock(void)
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{
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__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
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__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
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}
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#ifdef CONFIG_SOC_K2L
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void osr_init(void)
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{
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u32 i;
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u32 j;
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u32 val;
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u32 base = KS2_OSR_CFG_BASE;
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u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
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/* Enable the OSR clock domain */
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psc_enable_module(KS2_LPSC_OSR);
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/* Disable OSR ECC check for all the ram banks */
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for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
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val = i | KS2_OSR_ECC_VEC_TRIG_RD |
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(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
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writel(val , base + KS2_OSR_ECC_VEC);
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/**
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* wait till read is done.
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* Print should be added after earlyprintk support is added.
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*/
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for (j = 0; j < 10000; j++) {
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val = readl(base + KS2_OSR_ECC_VEC);
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if (val & KS2_OSR_ECC_VEC_RD_DONE)
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break;
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}
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ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
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KS2_OSR_ECC_CTRL_CHK;
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writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
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writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
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}
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/* Reset OSR memory to all zeros */
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for (i = 0; i < KS2_OSR_SIZE; i += 4)
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writel(0, KS2_OSR_DATA_BASE + i);
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/* Enable OSR ECC check for all the ram banks */
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for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
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writel(ecc_ctrl[i] |
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KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
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}
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#endif
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/* Function to set up PCIe mode */
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static void config_pcie_mode(int pcie_port, enum pci_mode mode)
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{
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u32 val = __raw_readl(KS2_DEVCFG);
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if (pcie_port >= MAX_PCI_PORTS)
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return;
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/**
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* each pci port has two bits for mode and it starts at
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* bit 1. So use port number to get the right bit position.
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*/
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pcie_port <<= 1;
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val &= ~(DEVCFG_MODE_MASK << pcie_port);
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val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
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__raw_writel(val, KS2_DEVCFG);
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}
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int arch_cpu_init(void)
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{
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chip_configuration_unlock();
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icache_enable();
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msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
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msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
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msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
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msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
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/* Initialize the PCIe-0 to work as Root Complex */
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config_pcie_mode(0, ROOTCOMPLEX);
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#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
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msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
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/* Initialize the PCIe-1 to work as Root Complex */
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config_pcie_mode(1, ROOTCOMPLEX);
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#endif
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#ifdef CONFIG_SOC_K2L
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osr_init();
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#endif
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/*
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* just initialise the COM2 port so that TI specific
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* UART register PWREMU_MGMT is initialized. Linux UART
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* driver doesn't handle this.
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*/
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NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
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u32 tmp;
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tmp = *rstctrl & KS2_RSTCTRL_MASK;
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*rstctrl = tmp | KS2_RSTCTRL_KEY;
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*rstctrl &= KS2_RSTCTRL_SWRST;
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for (;;)
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;
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}
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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#endif
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}
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