107 lines
1.9 KiB
C
107 lines
1.9 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/u-boot-x86.h>
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#include <flash.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/mtrr.h>
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#include <asm/arch/tables.h>
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#include <asm/arch/sysinfo.h>
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#include <asm/arch/timestamp.h>
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DECLARE_GLOBAL_DATA_PTR;
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int arch_cpu_init(void)
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{
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int ret = get_coreboot_info(&lib_sysinfo);
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if (ret != 0) {
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printf("Failed to parse coreboot tables.\n");
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return ret;
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}
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timestamp_init();
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return x86_cpu_init_f();
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int print_cpuinfo(void)
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{
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return default_print_cpuinfo();
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}
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int last_stage_init(void)
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{
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if (gd->flags & GD_FLG_COLD_BOOT)
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timestamp_add_to_bootstage();
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return 0;
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}
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#ifndef CONFIG_SYS_NO_FLASH
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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return 0;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void board_final_cleanup(void)
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{
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/* Un-cache the ROM so the kernel has one
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* more MTRR available.
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*
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* Coreboot should have assigned this to the
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* top available variable MTRR.
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*/
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u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
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u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
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/* Make sure this MTRR is the correct Write-Protected type */
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if (top_type == MTRR_TYPE_WRPROT) {
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struct mtrr_state state;
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mtrr_open(&state);
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wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
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wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
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mtrr_close(&state);
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}
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/* Issue SMI to Coreboot to lock down ME and registers */
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printf("Finalizing Coreboot\n");
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outb(0xcb, 0xb2);
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}
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void panic_puts(const char *str)
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{
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NS16550_t port = (NS16550_t)0x3f8;
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NS16550_init(port, 1);
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while (*str)
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NS16550_putc(port, *str++);
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}
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int misc_init_r(void)
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{
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return 0;
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}
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