503 lines
13 KiB
ArmAsm
503 lines
13 KiB
ArmAsm
/*
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* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
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*
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* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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.globl _start
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_start: b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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_pad: .word 0x12345678 /* now 16*4=64 */
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.global _end_vect
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_end_vect:
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.balignl 16,0xdeadbeef
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************/
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_TEXT_BASE:
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.word TEXT_BASE
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.globl _armboot_start
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_armboot_start:
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.word _start
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0xd3
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msr cpsr,r0
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#if (CONFIG_OMAP34XX)
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/* Copy vectors to mask ROM indirect addr */
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adr r0, _start @ r0 <- current position of code
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add r0, r0, #4 @ skip reset vector
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mov r2, #64 @ r2 <- size to copy
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add r2, r0, r2 @ r2 <- source end address
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mov r1, #SRAM_OFFSET0 @ build vect addr
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mov r3, #SRAM_OFFSET1
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add r1, r1, r3
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mov r3, #SRAM_OFFSET2
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add r1, r1, r3
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next:
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ldmia r0!, {r3 - r10} @ copy from source address [r0]
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stmia r1!, {r3 - r10} @ copy to target address [r1]
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cmp r0, r2 @ until source end address [r2]
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bne next @ loop until equal */
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#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
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/* No need to copy/exec the clock code - DPLL adjust already done
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* in NAND/oneNAND Boot.
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*/
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bl cpy_clk_code @ put dpll adjust code behind vectors
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#endif /* NAND Boot */
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#endif
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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relocate: @ relocate U-Boot to RAM
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adr r0, _start @ r0 <- current position of code
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ldr r1, _TEXT_BASE @ test if we run from flash or RAM
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cmp r0, r1 @ don't reloc during debug
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beq stack_setup
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ldr r2, _armboot_start
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ldr r3, _bss_start
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sub r2, r3, r2 @ r2 <- size of armboot
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add r2, r0, r2 @ r2 <- source end address
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copy_loop: @ copy 32 bytes at a time
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ldmia r0!, {r3 - r10} @ copy from source address [r0]
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stmia r1!, {r3 - r10} @ copy to target address [r1]
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cmp r0, r2 @ until source end addreee [r2]
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ble copy_loop
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#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
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/* Set up the stack */
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stack_setup:
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ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
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sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
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sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
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#ifdef CONFIG_USE_IRQ
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
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#endif
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sub sp, r0, #12 @ leave 3 words for abort-stack
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and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
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/* Clear BSS (if any). Is below tx (watch load addr - need space) */
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clear_bss:
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ldr r0, _bss_start @ find start of bss segment
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ldr r1, _bss_end @ stop here
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mov r2, #0x00000000 @ clear value
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clbss_l:
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str r2, [r0] @ clear BSS location
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cmp r0, r1 @ are we at the end yet
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add r0, r0, #4 @ increment clear index pointer
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bne clbss_l @ keep clearing till at end
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ldr pc, _start_armboot @ jump to C code
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_start_armboot: .word start_armboot
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/*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************/
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cpu_init_crit:
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/*
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* Invalidate L1 I/D
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*/
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Jump to board specific initialization...
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* The Mask ROM will have already initialized
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* basic memory. Go here to bump up clock rate and handle
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* wake up conditions.
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*/
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mov ip, lr @ persevere link reg across call
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bl lowlevel_init @ go setup pll,mux,memory
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mov lr, ip @ restore link
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mov pc, lr @ back to my caller
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
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@ user stack
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stmia sp, {r0 - r12} @ Save user registers (now in
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@ svc mode) r0-r12
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ldr r2, _armboot_start
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sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
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sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
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@ stack
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ldmia r2, {r2 - r3} @ get values for "aborted" pc
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@ and cpsr (into parm regs)
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add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp @ save current stack into r0
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@ (param register)
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
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@ a reserved stack spot would
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@ be good.
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into
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@ cpsr
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.endm
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.macro get_bad_stack
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ldr r13, _armboot_start @ setup our mode stack (enter
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@ in banked mode)
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sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
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sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
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@ spots for abort stack
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str lr, [r13] @ save caller lr in position 0
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@ of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r13, #4] @ save spsr in position 1 of
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@ saved stack
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13 @ switch modes, make sure
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@ moves will execute
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mov lr, pc @ capture return pc
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movs pc, lr @ jump to next instruction &
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@ switch modes.
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.endm
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.macro get_bad_stack_swi
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sub r13, r13, #4 @ space on current stack for
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@ scratch reg.
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str r0, [r13] @ save R0's value.
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ldr r0, _armboot_start @ get data regions start
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sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
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sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
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@ spots for abort stack
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str lr, [r0] @ save caller lr in position 0
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@ of saved stack
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mrs r0, spsr @ get the spsr
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str lr, [r0, #4] @ save spsr in position 1 of
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@ saved stack
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ldr r0, [r13] @ restore r0
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add r13, r13, #4 @ pop stack entry
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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*/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack_swi
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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/* someone ought to write a more effective fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r5, r7, r9-r11
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*
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* - mm - mm_struct describing address space
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*/
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.align 5
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.global v7_flush_dcache_all
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v7_flush_dcache_all:
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stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
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mov r7, r0 @ take a backup of device type
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cmp r0, #0x3 @ check if the device type is
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@ GP
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moveq r12, #0x1 @ set up to invalide L2
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smi: .word 0x01600070 @ Call SMI monitor (smieq)
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cmp r7, #0x3 @ compare again in case its
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@ lost
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beq finished_inval @ if GP device, inval done
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@ above
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished_inval @ if loc is 0, then no need to
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@ clean
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mov r10, #0 @ start clean at cache level 0
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inval_loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache
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@ level
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mov r1, r0, lsr r2 @ extract cache type bits from
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@ clidr
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and r1, r1, #7 @ mask of the bits for current
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@ cache only
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cmp r1, #2 @ see what cache we have at
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@ this level
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blt skip_inval @ skip if no cache, or just
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@ i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mov r2, #0 @ operand for mcr SBZ
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mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
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@ sych the new cssr&csidr,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the
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@ cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the
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@ way size
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clz r5, r4 @ find bit position of way
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@ size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the
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@ index size
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inval_loop2:
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mov r9, r4 @ create working copy of max
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@ way size
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inval_loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number
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@ into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge inval_loop3
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subs r7, r7, #1 @ decrement the index
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bge inval_loop2
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skip_inval:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt inval_loop1
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finished_inval:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
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