474 lines
11 KiB
C
474 lines
11 KiB
C
/*
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* generic mmc spi driver
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*
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <stdlib.h>
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#include <linux/bitops.h>
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#include <u-boot/crc.h>
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#include <linux/crc7.h>
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#include <asm/byteorder.h>
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#include <dm.h>
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#include <spi.h>
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/* MMC/SD in SPI mode reports R1 status always */
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#define R1_SPI_IDLE BIT(0)
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#define R1_SPI_ERASE_RESET BIT(1)
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#define R1_SPI_ILLEGAL_COMMAND BIT(2)
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#define R1_SPI_COM_CRC BIT(3)
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#define R1_SPI_ERASE_SEQ BIT(4)
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#define R1_SPI_ADDRESS BIT(5)
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#define R1_SPI_PARAMETER BIT(6)
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/* R1 bit 7 is always zero, reuse this bit for error */
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#define R1_SPI_ERROR BIT(7)
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/* Response tokens used to ack each block written: */
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#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
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#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
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#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
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#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
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/* Read and write blocks start with these tokens and end with crc;
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* on error, read tokens act like a subset of R2_SPI_* values.
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*/
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/* single block write multiblock read */
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#define SPI_TOKEN_SINGLE 0xfe
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/* multiblock write */
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#define SPI_TOKEN_MULTI_WRITE 0xfc
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/* terminate multiblock write */
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#define SPI_TOKEN_STOP_TRAN 0xfd
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/* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
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#define MMC_SPI_CMD(x) (0x40 | (x))
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/* bus capability */
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#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
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#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
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#define MMC_SPI_MAX_CLOCK 25000000 /* SD/MMC legacy speed */
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/* timeout value */
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#define CMD_TIMEOUT 8
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#define READ_TIMEOUT 3000000 /* 1 sec */
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#define WRITE_TIMEOUT 3000000 /* 1 sec */
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#define R1B_TIMEOUT 3000000 /* 1 sec */
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struct mmc_spi_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct mmc_spi_priv {
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struct spi_slave *spi;
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};
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static int mmc_spi_sendcmd(struct udevice *dev,
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ushort cmdidx, u32 cmdarg, u32 resp_type,
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u8 *resp, u32 resp_size,
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bool resp_match, u8 resp_match_value, bool r1b)
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{
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int i, rpos = 0, ret = 0;
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u8 cmdo[7], r;
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debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
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"resp_size=%d resp_match=%d resp_match_value=0x%x\n",
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__func__, cmdidx, cmdarg, resp_type,
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resp_size, resp_match, resp_match_value);
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cmdo[0] = 0xff;
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cmdo[1] = MMC_SPI_CMD(cmdidx);
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cmdo[2] = cmdarg >> 24;
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cmdo[3] = cmdarg >> 16;
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cmdo[4] = cmdarg >> 8;
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cmdo[5] = cmdarg;
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cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
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ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
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if (ret)
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return ret;
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ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
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if (ret)
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return ret;
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if (!resp || !resp_size)
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return 0;
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debug("%s: cmd%d", __func__, cmdidx);
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if (resp_match) {
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r = ~resp_match_value;
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i = CMD_TIMEOUT;
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while (i) {
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ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
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if (ret)
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return ret;
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debug(" resp%d=0x%x", rpos, r);
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rpos++;
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i--;
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if (r == resp_match_value)
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break;
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}
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if (!i && (r != resp_match_value))
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return -ETIMEDOUT;
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}
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for (i = 0; i < resp_size; i++) {
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if (i == 0 && resp_match) {
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resp[i] = resp_match_value;
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continue;
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}
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ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
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if (ret)
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return ret;
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debug(" resp%d=0x%x", rpos, r);
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rpos++;
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resp[i] = r;
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}
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if (r1b == true) {
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i = R1B_TIMEOUT;
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while (i) {
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ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
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if (ret)
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return ret;
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debug(" resp%d=0x%x", rpos, r);
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rpos++;
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i--;
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if (r)
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break;
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}
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if (!i)
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return -ETIMEDOUT;
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}
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debug("\n");
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return 0;
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}
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static int mmc_spi_readdata(struct udevice *dev,
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void *xbuf, u32 bcnt, u32 bsize)
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{
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u16 crc;
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u8 *buf = xbuf, r1;
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int i, ret = 0;
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while (bcnt--) {
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for (i = 0; i < READ_TIMEOUT; i++) {
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ret = dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
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if (ret)
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return ret;
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if (r1 == SPI_TOKEN_SINGLE)
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break;
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}
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debug("%s: data tok%d 0x%x\n", __func__, i, r1);
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if (r1 == SPI_TOKEN_SINGLE) {
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ret = dm_spi_xfer(dev, bsize * 8, NULL, buf, 0);
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if (ret)
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return ret;
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ret = dm_spi_xfer(dev, 2 * 8, NULL, &crc, 0);
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if (ret)
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return ret;
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#ifdef CONFIG_MMC_SPI_CRC_ON
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if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
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debug("%s: data crc error\n", __func__);
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r1 = R1_SPI_COM_CRC;
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break;
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}
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#endif
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r1 = 0;
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} else {
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r1 = R1_SPI_ERROR;
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break;
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}
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buf += bsize;
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}
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if (r1 & R1_SPI_COM_CRC)
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ret = -ECOMM;
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else if (r1) /* other errors */
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ret = -ETIMEDOUT;
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return ret;
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}
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static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
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u32 bcnt, u32 bsize, int multi)
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{
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const u8 *buf = xbuf;
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u8 r1, tok[2];
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u16 crc;
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int i, ret = 0;
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tok[0] = 0xff;
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tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
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while (bcnt--) {
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#ifdef CONFIG_MMC_SPI_CRC_ON
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crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
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#endif
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dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
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dm_spi_xfer(dev, bsize * 8, buf, NULL, 0);
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dm_spi_xfer(dev, 2 * 8, &crc, NULL, 0);
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for (i = 0; i < CMD_TIMEOUT; i++) {
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dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
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if ((r1 & 0x10) == 0) /* response token */
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break;
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}
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debug("%s: data tok%d 0x%x\n", __func__, i, r1);
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if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
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debug("%s: data accepted\n", __func__);
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for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
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dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
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if (i && r1 == 0xff) {
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r1 = 0;
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break;
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}
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}
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if (i == WRITE_TIMEOUT) {
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debug("%s: data write timeout 0x%x\n",
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__func__, r1);
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r1 = R1_SPI_ERROR;
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break;
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}
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} else {
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debug("%s: data error 0x%x\n", __func__, r1);
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r1 = R1_SPI_COM_CRC;
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break;
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}
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buf += bsize;
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}
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if (multi && bcnt == -1) { /* stop multi write */
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tok[1] = SPI_TOKEN_STOP_TRAN;
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dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
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for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
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dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
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if (i && r1 == 0xff) {
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r1 = 0;
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break;
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}
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}
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if (i == WRITE_TIMEOUT) {
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debug("%s: data write timeout 0x%x\n", __func__, r1);
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r1 = R1_SPI_ERROR;
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}
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}
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if (r1 & R1_SPI_COM_CRC)
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ret = -ECOMM;
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else if (r1) /* other errors */
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ret = -ETIMEDOUT;
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return ret;
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}
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static int dm_mmc_spi_set_ios(struct udevice *dev)
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{
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return 0;
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}
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static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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int i, multi, ret = 0;
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u8 *resp = NULL;
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u32 resp_size = 0;
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bool resp_match = false, r1b = false;
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u8 resp8 = 0, resp16[2] = { 0 }, resp40[5] = { 0 }, resp_match_value = 0;
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dm_spi_claim_bus(dev);
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for (i = 0; i < 4; i++)
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cmd->response[i] = 0;
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switch (cmd->cmdidx) {
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case SD_CMD_APP_SEND_OP_COND:
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case MMC_CMD_SEND_OP_COND:
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resp = &resp8;
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resp_size = sizeof(resp8);
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cmd->cmdarg = 0x40000000;
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break;
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case SD_CMD_SEND_IF_COND:
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resp = (u8 *)&resp40[0];
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resp_size = sizeof(resp40);
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resp_match = true;
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resp_match_value = R1_SPI_IDLE;
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break;
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case MMC_CMD_SPI_READ_OCR:
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resp = (u8 *)&resp40[0];
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resp_size = sizeof(resp40);
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break;
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case MMC_CMD_SEND_STATUS:
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resp = (u8 *)&resp16[0];
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resp_size = sizeof(resp16);
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break;
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case MMC_CMD_SET_BLOCKLEN:
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case MMC_CMD_SPI_CRC_ON_OFF:
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resp = &resp8;
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resp_size = sizeof(resp8);
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resp_match = true;
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resp_match_value = 0x0;
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break;
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case MMC_CMD_STOP_TRANSMISSION:
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case MMC_CMD_ERASE:
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resp = &resp8;
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resp_size = sizeof(resp8);
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r1b = true;
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break;
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case MMC_CMD_SEND_CSD:
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case MMC_CMD_SEND_CID:
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case MMC_CMD_READ_SINGLE_BLOCK:
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case MMC_CMD_READ_MULTIPLE_BLOCK:
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case MMC_CMD_WRITE_SINGLE_BLOCK:
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case MMC_CMD_WRITE_MULTIPLE_BLOCK:
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case MMC_CMD_APP_CMD:
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case SD_CMD_ERASE_WR_BLK_START:
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case SD_CMD_ERASE_WR_BLK_END:
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resp = &resp8;
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resp_size = sizeof(resp8);
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break;
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default:
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resp = &resp8;
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resp_size = sizeof(resp8);
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resp_match = true;
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resp_match_value = R1_SPI_IDLE;
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break;
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};
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ret = mmc_spi_sendcmd(dev, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
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resp, resp_size, resp_match, resp_match_value, r1b);
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if (ret)
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goto done;
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switch (cmd->cmdidx) {
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case SD_CMD_APP_SEND_OP_COND:
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case MMC_CMD_SEND_OP_COND:
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cmd->response[0] = (resp8 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
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break;
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case SD_CMD_SEND_IF_COND:
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case MMC_CMD_SPI_READ_OCR:
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cmd->response[0] = resp40[4];
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cmd->response[0] |= (uint)resp40[3] << 8;
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cmd->response[0] |= (uint)resp40[2] << 16;
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cmd->response[0] |= (uint)resp40[1] << 24;
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break;
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case MMC_CMD_SEND_STATUS:
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if (resp16[0] || resp16[1])
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cmd->response[0] = MMC_STATUS_ERROR;
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else
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cmd->response[0] = MMC_STATUS_RDY_FOR_DATA;
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break;
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case MMC_CMD_SEND_CID:
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case MMC_CMD_SEND_CSD:
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ret = mmc_spi_readdata(dev, cmd->response, 1, 16);
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if (ret)
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return ret;
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for (i = 0; i < 4; i++)
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cmd->response[i] =
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cpu_to_be32(cmd->response[i]);
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break;
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default:
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cmd->response[0] = resp8;
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break;
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}
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debug("%s: cmd%d resp0=0x%x resp1=0x%x resp2=0x%x resp3=0x%x\n",
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__func__, cmd->cmdidx, cmd->response[0], cmd->response[1],
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cmd->response[2], cmd->response[3]);
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if (data) {
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debug("%s: data flags=0x%x blocks=%d block_size=%d\n",
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__func__, data->flags, data->blocks, data->blocksize);
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multi = (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK);
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if (data->flags == MMC_DATA_READ)
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ret = mmc_spi_readdata(dev, data->dest,
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data->blocks, data->blocksize);
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else if (data->flags == MMC_DATA_WRITE)
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ret = mmc_spi_writedata(dev, data->src,
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data->blocks, data->blocksize,
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multi);
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}
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done:
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dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
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dm_spi_release_bus(dev);
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return ret;
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}
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static int mmc_spi_probe(struct udevice *dev)
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{
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struct mmc_spi_priv *priv = dev_get_priv(dev);
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struct mmc_spi_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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char *name;
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priv->spi = dev_get_parent_priv(dev);
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if (!priv->spi->max_hz)
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priv->spi->max_hz = MMC_SPI_MAX_CLOCK;
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priv->spi->speed = 0;
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priv->spi->mode = SPI_MODE_0;
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priv->spi->wordlen = 8;
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name = malloc(strlen(dev->parent->name) + strlen(dev->name) + 4);
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if (!name)
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return -ENOMEM;
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sprintf(name, "%s:%s", dev->parent->name, dev->name);
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plat->cfg.name = name;
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plat->cfg.host_caps = MMC_MODE_SPI;
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plat->cfg.voltages = MMC_SPI_VOLTAGE;
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plat->cfg.f_min = MMC_SPI_MIN_CLOCK;
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plat->cfg.f_max = priv->spi->max_hz;
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plat->cfg.part_type = PART_TYPE_DOS;
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plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
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plat->mmc.cfg = &plat->cfg;
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plat->mmc.priv = priv;
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plat->mmc.dev = dev;
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upriv->mmc = &plat->mmc;
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return 0;
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}
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static int mmc_spi_bind(struct udevice *dev)
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{
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struct mmc_spi_plat *plat = dev_get_platdata(dev);
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return mmc_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct dm_mmc_ops mmc_spi_ops = {
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.send_cmd = dm_mmc_spi_request,
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.set_ios = dm_mmc_spi_set_ios,
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};
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static const struct udevice_id dm_mmc_spi_match[] = {
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{ .compatible = "mmc-spi-slot" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(mmc_spi) = {
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.name = "mmc_spi",
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.id = UCLASS_MMC,
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.of_match = dm_mmc_spi_match,
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.ops = &mmc_spi_ops,
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.probe = mmc_spi_probe,
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.bind = mmc_spi_bind,
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.platdata_auto_alloc_size = sizeof(struct mmc_spi_plat),
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.priv_auto_alloc_size = sizeof(struct mmc_spi_priv),
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};
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