81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/wdt.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
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void reset_cpu(ulong addr)
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{
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/* Enable watchdog clock */
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setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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/* To be compatible with the original U-Boot code:
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* addr: - 0: perform hard reset.
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* - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
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if (addr == 0) {
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/* Reset pulse length is 13005 peripheral clock frames */
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writel(13000, &wdt->pulse);
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/* Force WDOG_RESET2 and RESOUT_N signal active */
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writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
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| WDTIM_MCTRL_M_RES2, &wdt->mctrl);
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} else {
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/* Force match output active */
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writel(0x01, &wdt->emr);
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/* Internal reset on match output (no pulse on "RESOUT_N") */
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writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
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}
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while (1)
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/* NOP */;
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}
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#if defined(CONFIG_ARCH_CPU_INIT)
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int arch_cpu_init(void)
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{
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/*
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* It might be necessary to flush data cache, if U-Boot is loaded
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* from kickstart bootloader, e.g. from S1L loader
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*/
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flush_dcache_all();
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return 0;
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}
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#else
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#error "You have to select CONFIG_ARCH_CPU_INIT"
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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printf("CPU: NXP LPC32XX\n");
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printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
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printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
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printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
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return 0;
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}
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#endif
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#ifdef CONFIG_LPC32XX_ETH
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int cpu_eth_init(struct bd_info *bis)
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{
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lpc32xx_eth_initialize(bis);
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return 0;
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}
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#endif
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