926 lines
24 KiB
C
926 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
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* (C) Copyright 2018 - BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/arch/clock-gx.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dt-bindings/clock/gxbb-clkc.h>
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#include <linux/bitops.h>
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#include "clk_meson.h"
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#include <linux/err.h>
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/* This driver support only basic clock tree operations :
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* - Can calculate clock frequency on a limited tree
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* - Can Read muxes and basic dividers (0-based only)
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* - Can enable/disable gates with limited propagation
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* - Can reparent without propagation, only on muxes
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* - Can set rates without reparenting
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* This driver is adapted to what is actually supported by U-Boot
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*/
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/* Only the clocks ids we don't want to expose, such as the internal muxes
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* and dividers of composite clocks, will remain defined here.
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*/
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#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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#define CLKID_SAR_ADC_DIV 99
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#define CLKID_MALI_0_DIV 101
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#define CLKID_MALI_1_DIV 104
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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#define CLKID_32K_CLK_SEL 115
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#define CLKID_32K_CLK_DIV 116
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#define CLKID_SD_EMMC_A_CLK0_SEL 117
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#define CLKID_SD_EMMC_A_CLK0_DIV 118
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#define CLKID_SD_EMMC_B_CLK0_SEL 120
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#define CLKID_SD_EMMC_B_CLK0_DIV 121
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#define CLKID_SD_EMMC_C_CLK0_SEL 123
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#define CLKID_SD_EMMC_C_CLK0_DIV 124
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#define CLKID_VPU_0_DIV 127
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#define CLKID_VPU_1_DIV 130
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#define CLKID_VAPB_0_DIV 134
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#define CLKID_VAPB_1_DIV 137
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#define CLKID_HDMI_PLL_PRE_MULT 141
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#define CLKID_MPLL0_DIV 142
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#define CLKID_MPLL1_DIV 143
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#define CLKID_MPLL2_DIV 144
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#define CLKID_MPLL_PREDIV 145
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#define CLKID_FCLK_DIV2_DIV 146
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#define CLKID_FCLK_DIV3_DIV 147
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#define CLKID_FCLK_DIV4_DIV 148
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#define CLKID_FCLK_DIV5_DIV 149
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#define CLKID_FCLK_DIV7_DIV 150
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#define CLKID_VDEC_1_SEL 151
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#define CLKID_VDEC_1_DIV 152
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#define CLKID_VDEC_HEVC_SEL 154
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#define CLKID_VDEC_HEVC_DIV 155
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#define XTAL_RATE 24000000
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struct meson_clk {
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struct regmap *map;
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};
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static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
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static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
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ulong current_rate);
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static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
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unsigned long parent_id);
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static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
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static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
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ulong rate, ulong current_rate);
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static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
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static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
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static struct meson_gate gates[] = {
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/* Everything Else (EE) domain gates */
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MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
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MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
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MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5),
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MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6),
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MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7),
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MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8),
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MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
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MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10),
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MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11),
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MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12),
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MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
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MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14),
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MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15),
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MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16),
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MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17),
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MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18),
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MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19),
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MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23),
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MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24),
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MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
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MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
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MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30),
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MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2),
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MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
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MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4),
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MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6),
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MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7),
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MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8),
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MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9),
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MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10),
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MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11),
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MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12),
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MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13),
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MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14),
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MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15),
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MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
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MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20),
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MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21),
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MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22),
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MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23),
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MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24),
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MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25),
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MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26),
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MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28),
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MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29),
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MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30),
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MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31),
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MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
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MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
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MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
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MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
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MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
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MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
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MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
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MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
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MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
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MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
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MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
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MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26),
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MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29),
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MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1),
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MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2),
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MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3),
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MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4),
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MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8),
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MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10),
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MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14),
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MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16),
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MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20),
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MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21),
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MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22),
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MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24),
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MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25),
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MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26),
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MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31),
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/* Always On (AO) domain gates */
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MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0),
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MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1),
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MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2),
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MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3),
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MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
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/* PLL Gates */
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/* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
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MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
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MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
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MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
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MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),
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MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
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MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
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MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
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/* CLKID_CLK81 is critical for the system */
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/* Peripheral Gates */
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MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8),
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MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
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MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
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MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
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MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
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MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
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MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
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MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
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MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
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};
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static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct meson_gate *gate;
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debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
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/* Propagate through muxes */
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switch (id) {
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case CLKID_VPU:
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return meson_set_gate_by_id(clk,
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meson_mux_get_parent(clk, CLKID_VPU), on);
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case CLKID_VAPB_SEL:
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return meson_set_gate_by_id(clk,
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meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
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}
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if (id >= ARRAY_SIZE(gates))
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return -ENOENT;
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gate = &gates[id];
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if (gate->reg == 0)
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return 0;
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debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
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regmap_update_bits(priv->map, gate->reg,
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BIT(gate->bit), on ? BIT(gate->bit) : 0);
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/* Propagate to next gate(s) */
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switch (id) {
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case CLKID_VAPB:
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return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
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}
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return 0;
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}
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static int meson_clk_enable(struct clk *clk)
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{
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return meson_set_gate_by_id(clk, clk->id, true);
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}
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static int meson_clk_disable(struct clk *clk)
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{
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return meson_set_gate_by_id(clk, clk->id, false);
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}
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static struct parm meson_vpu_0_div_parm = {
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HHI_VPU_CLK_CNTL, 0, 7,
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};
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int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
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static struct parm meson_vpu_1_div_parm = {
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HHI_VPU_CLK_CNTL, 16, 7,
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};
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int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
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static struct parm meson_vapb_0_div_parm = {
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HHI_VAPBCLK_CNTL, 0, 7,
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};
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int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
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static struct parm meson_vapb_1_div_parm = {
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HHI_VAPBCLK_CNTL, 16, 7,
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};
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int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
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static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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unsigned int rate, parent_rate;
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struct parm *parm;
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int parent;
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uint reg;
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switch (id) {
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case CLKID_VPU_0_DIV:
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parm = &meson_vpu_0_div_parm;
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parent = meson_vpu_0_div_parent;
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break;
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case CLKID_VPU_1_DIV:
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parm = &meson_vpu_1_div_parm;
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parent = meson_vpu_1_div_parent;
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break;
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case CLKID_VAPB_0_DIV:
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parm = &meson_vapb_0_div_parm;
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parent = meson_vapb_0_div_parent;
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break;
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case CLKID_VAPB_1_DIV:
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parm = &meson_vapb_1_div_parm;
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parent = meson_vapb_1_div_parent;
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break;
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default:
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return -ENOENT;
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}
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regmap_read(priv->map, parm->reg_off, ®);
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reg = PARM_GET(parm->width, parm->shift, reg);
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debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
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parent_rate = meson_clk_get_rate_by_id(clk, parent);
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
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rate = parent_rate / (reg + 1);
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debug("%s: rate of %ld is %d\n", __func__, id, rate);
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return rate;
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}
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static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
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ulong current_rate)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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unsigned int new_div = -EINVAL;
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unsigned long parent_rate;
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struct parm *parm;
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int parent;
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int ret;
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if (current_rate == rate)
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return 0;
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debug("%s: setting rate of %ld from %ld to %ld\n",
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__func__, id, current_rate, rate);
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switch (id) {
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case CLKID_VPU_0_DIV:
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parm = &meson_vpu_0_div_parm;
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parent = meson_vpu_0_div_parent;
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break;
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case CLKID_VPU_1_DIV:
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parm = &meson_vpu_1_div_parm;
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parent = meson_vpu_1_div_parent;
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break;
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case CLKID_VAPB_0_DIV:
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parm = &meson_vapb_0_div_parm;
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parent = meson_vapb_0_div_parent;
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break;
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case CLKID_VAPB_1_DIV:
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parm = &meson_vapb_1_div_parm;
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parent = meson_vapb_1_div_parent;
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break;
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default:
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return -ENOENT;
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}
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parent_rate = meson_clk_get_rate_by_id(clk, parent);
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
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/* If can't divide, set parent instead */
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if (!parent_rate || rate > parent_rate)
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return meson_clk_set_rate_by_id(clk, parent, rate,
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current_rate);
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new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
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debug("%s: new div of %ld is %d\n", __func__, id, new_div);
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/* If overflow, try to set parent rate and retry */
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if (!new_div || new_div > (1 << parm->width)) {
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ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
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if (IS_ERR_VALUE(ret))
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return ret;
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parent_rate = meson_clk_get_rate_by_id(clk, parent);
|
|
if (IS_ERR_VALUE(parent_rate))
|
|
return parent_rate;
|
|
|
|
new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
|
|
|
debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
|
|
|
|
if (!new_div || new_div > (1 << parm->width))
|
|
return -EINVAL;
|
|
}
|
|
|
|
debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
|
|
|
|
regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
|
|
(new_div - 1) << parm->shift);
|
|
|
|
debug("%s: new rate of %ld is %ld\n",
|
|
__func__, id, meson_div_get_rate(clk, id));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct parm meson_vpu_mux_parm = {
|
|
HHI_VPU_CLK_CNTL, 31, 1,
|
|
};
|
|
|
|
int meson_vpu_mux_parents[] = {
|
|
CLKID_VPU_0,
|
|
CLKID_VPU_1,
|
|
};
|
|
|
|
static struct parm meson_vpu_0_mux_parm = {
|
|
HHI_VPU_CLK_CNTL, 9, 2,
|
|
};
|
|
|
|
static struct parm meson_vpu_1_mux_parm = {
|
|
HHI_VPU_CLK_CNTL, 25, 2,
|
|
};
|
|
|
|
static int meson_vpu_0_1_mux_parents[] = {
|
|
CLKID_FCLK_DIV4,
|
|
CLKID_FCLK_DIV3,
|
|
CLKID_FCLK_DIV5,
|
|
CLKID_FCLK_DIV7,
|
|
};
|
|
|
|
static struct parm meson_vapb_sel_mux_parm = {
|
|
HHI_VAPBCLK_CNTL, 31, 1,
|
|
};
|
|
|
|
int meson_vapb_sel_mux_parents[] = {
|
|
CLKID_VAPB_0,
|
|
CLKID_VAPB_1,
|
|
};
|
|
|
|
static struct parm meson_vapb_0_mux_parm = {
|
|
HHI_VAPBCLK_CNTL, 9, 2,
|
|
};
|
|
|
|
static struct parm meson_vapb_1_mux_parm = {
|
|
HHI_VAPBCLK_CNTL, 25, 2,
|
|
};
|
|
|
|
static int meson_vapb_0_1_mux_parents[] = {
|
|
CLKID_FCLK_DIV4,
|
|
CLKID_FCLK_DIV3,
|
|
CLKID_FCLK_DIV5,
|
|
CLKID_FCLK_DIV7,
|
|
};
|
|
|
|
static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
|
|
{
|
|
struct meson_clk *priv = dev_get_priv(clk->dev);
|
|
struct parm *parm;
|
|
int *parents;
|
|
uint reg;
|
|
|
|
switch (id) {
|
|
case CLKID_VPU:
|
|
parm = &meson_vpu_mux_parm;
|
|
parents = meson_vpu_mux_parents;
|
|
break;
|
|
case CLKID_VPU_0_SEL:
|
|
parm = &meson_vpu_0_mux_parm;
|
|
parents = meson_vpu_0_1_mux_parents;
|
|
break;
|
|
case CLKID_VPU_1_SEL:
|
|
parm = &meson_vpu_1_mux_parm;
|
|
parents = meson_vpu_0_1_mux_parents;
|
|
break;
|
|
case CLKID_VAPB_SEL:
|
|
parm = &meson_vapb_sel_mux_parm;
|
|
parents = meson_vapb_sel_mux_parents;
|
|
break;
|
|
case CLKID_VAPB_0_SEL:
|
|
parm = &meson_vapb_0_mux_parm;
|
|
parents = meson_vapb_0_1_mux_parents;
|
|
break;
|
|
case CLKID_VAPB_1_SEL:
|
|
parm = &meson_vapb_1_mux_parm;
|
|
parents = meson_vapb_0_1_mux_parents;
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
regmap_read(priv->map, parm->reg_off, ®);
|
|
reg = PARM_GET(parm->width, parm->shift, reg);
|
|
|
|
debug("%s: parent of %ld is %d (%d)\n",
|
|
__func__, id, parents[reg], reg);
|
|
|
|
return parents[reg];
|
|
}
|
|
|
|
static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
|
|
unsigned long parent_id)
|
|
{
|
|
unsigned long cur_parent = meson_mux_get_parent(clk, id);
|
|
struct meson_clk *priv = dev_get_priv(clk->dev);
|
|
unsigned int new_index = -EINVAL;
|
|
struct parm *parm;
|
|
int *parents;
|
|
int i;
|
|
|
|
if (IS_ERR_VALUE(cur_parent))
|
|
return cur_parent;
|
|
|
|
debug("%s: setting parent of %ld from %ld to %ld\n",
|
|
__func__, id, cur_parent, parent_id);
|
|
|
|
if (cur_parent == parent_id)
|
|
return 0;
|
|
|
|
switch (id) {
|
|
case CLKID_VPU:
|
|
parm = &meson_vpu_mux_parm;
|
|
parents = meson_vpu_mux_parents;
|
|
break;
|
|
case CLKID_VPU_0_SEL:
|
|
parm = &meson_vpu_0_mux_parm;
|
|
parents = meson_vpu_0_1_mux_parents;
|
|
break;
|
|
case CLKID_VPU_1_SEL:
|
|
parm = &meson_vpu_1_mux_parm;
|
|
parents = meson_vpu_0_1_mux_parents;
|
|
break;
|
|
case CLKID_VAPB_SEL:
|
|
parm = &meson_vapb_sel_mux_parm;
|
|
parents = meson_vapb_sel_mux_parents;
|
|
break;
|
|
case CLKID_VAPB_0_SEL:
|
|
parm = &meson_vapb_0_mux_parm;
|
|
parents = meson_vapb_0_1_mux_parents;
|
|
break;
|
|
case CLKID_VAPB_1_SEL:
|
|
parm = &meson_vapb_1_mux_parm;
|
|
parents = meson_vapb_0_1_mux_parents;
|
|
break;
|
|
default:
|
|
/* Not a mux */
|
|
return -ENOENT;
|
|
}
|
|
|
|
for (i = 0 ; i < (1 << parm->width) ; ++i) {
|
|
if (parents[i] == parent_id)
|
|
new_index = i;
|
|
}
|
|
|
|
if (IS_ERR_VALUE(new_index))
|
|
return new_index;
|
|
|
|
debug("%s: new index of %ld is %d\n", __func__, id, new_index);
|
|
|
|
regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
|
|
new_index << parm->shift);
|
|
|
|
debug("%s: new parent of %ld is %ld\n",
|
|
__func__, id, meson_mux_get_parent(clk, id));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
|
|
{
|
|
int parent = meson_mux_get_parent(clk, id);
|
|
|
|
if (IS_ERR_VALUE(parent))
|
|
return parent;
|
|
|
|
return meson_clk_get_rate_by_id(clk, parent);
|
|
}
|
|
|
|
static unsigned long meson_clk81_get_rate(struct clk *clk)
|
|
{
|
|
struct meson_clk *priv = dev_get_priv(clk->dev);
|
|
unsigned long parent_rate;
|
|
uint reg;
|
|
int parents[] = {
|
|
-1,
|
|
-1,
|
|
CLKID_FCLK_DIV7,
|
|
CLKID_MPLL1,
|
|
CLKID_MPLL2,
|
|
CLKID_FCLK_DIV4,
|
|
CLKID_FCLK_DIV3,
|
|
CLKID_FCLK_DIV5
|
|
};
|
|
|
|
/* mux */
|
|
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
|
|
reg = (reg >> 12) & 7;
|
|
|
|
switch (reg) {
|
|
case 0:
|
|
parent_rate = XTAL_RATE;
|
|
break;
|
|
case 1:
|
|
return -ENOENT;
|
|
default:
|
|
parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
|
|
}
|
|
|
|
/* divider */
|
|
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
|
|
reg = reg & ((1 << 7) - 1);
|
|
|
|
/* clk81 divider is zero based */
|
|
return parent_rate / (reg + 1);
|
|
}
|
|
|
|
static long mpll_rate_from_params(unsigned long parent_rate,
|
|
unsigned long sdm,
|
|
unsigned long n2)
|
|
{
|
|
unsigned long divisor = (SDM_DEN * n2) + sdm;
|
|
|
|
if (n2 < N2_MIN)
|
|
return -EINVAL;
|
|
|
|
return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
|
|
}
|
|
|
|
static struct parm meson_mpll0_parm[3] = {
|
|
{HHI_MPLL_CNTL7, 0, 14}, /* psdm */
|
|
{HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
|
|
};
|
|
|
|
static struct parm meson_mpll1_parm[3] = {
|
|
{HHI_MPLL_CNTL8, 0, 14}, /* psdm */
|
|
{HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
|
|
};
|
|
|
|
static struct parm meson_mpll2_parm[3] = {
|
|
{HHI_MPLL_CNTL9, 0, 14}, /* psdm */
|
|
{HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
|
|
};
|
|
|
|
/*
|
|
* MultiPhase Locked Loops are outputs from a PLL with additional frequency
|
|
* scaling capabilities. MPLL rates are calculated as:
|
|
*
|
|
* f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
|
|
*/
|
|
static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
|
|
{
|
|
struct meson_clk *priv = dev_get_priv(clk->dev);
|
|
struct parm *psdm, *pn2;
|
|
unsigned long sdm, n2;
|
|
unsigned long parent_rate;
|
|
uint reg;
|
|
|
|
switch (id) {
|
|
case CLKID_MPLL0:
|
|
psdm = &meson_mpll0_parm[0];
|
|
pn2 = &meson_mpll0_parm[1];
|
|
break;
|
|
case CLKID_MPLL1:
|
|
psdm = &meson_mpll1_parm[0];
|
|
pn2 = &meson_mpll1_parm[1];
|
|
break;
|
|
case CLKID_MPLL2:
|
|
psdm = &meson_mpll2_parm[0];
|
|
pn2 = &meson_mpll2_parm[1];
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
|
|
if (IS_ERR_VALUE(parent_rate))
|
|
return parent_rate;
|
|
|
|
regmap_read(priv->map, psdm->reg_off, ®);
|
|
sdm = PARM_GET(psdm->width, psdm->shift, reg);
|
|
|
|
regmap_read(priv->map, pn2->reg_off, ®);
|
|
n2 = PARM_GET(pn2->width, pn2->shift, reg);
|
|
|
|
return mpll_rate_from_params(parent_rate, sdm, n2);
|
|
}
|
|
|
|
static struct parm meson_fixed_pll_parm[3] = {
|
|
{HHI_MPLL_CNTL, 0, 9}, /* pm */
|
|
{HHI_MPLL_CNTL, 9, 5}, /* pn */
|
|
{HHI_MPLL_CNTL, 16, 2}, /* pod */
|
|
};
|
|
|
|
static struct parm meson_sys_pll_parm[3] = {
|
|
{HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
|
|
{HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
|
|
{HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
|
|
};
|
|
|
|
static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
|
|
{
|
|
struct meson_clk *priv = dev_get_priv(clk->dev);
|
|
struct parm *pm, *pn, *pod;
|
|
unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
|
|
u16 n, m, od;
|
|
uint reg;
|
|
|
|
switch (id) {
|
|
case CLKID_FIXED_PLL:
|
|
pm = &meson_fixed_pll_parm[0];
|
|
pn = &meson_fixed_pll_parm[1];
|
|
pod = &meson_fixed_pll_parm[2];
|
|
break;
|
|
case CLKID_SYS_PLL:
|
|
pm = &meson_sys_pll_parm[0];
|
|
pn = &meson_sys_pll_parm[1];
|
|
pod = &meson_sys_pll_parm[2];
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
regmap_read(priv->map, pn->reg_off, ®);
|
|
n = PARM_GET(pn->width, pn->shift, reg);
|
|
|
|
regmap_read(priv->map, pm->reg_off, ®);
|
|
m = PARM_GET(pm->width, pm->shift, reg);
|
|
|
|
regmap_read(priv->map, pod->reg_off, ®);
|
|
od = PARM_GET(pod->width, pod->shift, reg);
|
|
|
|
return ((parent_rate_mhz * m / n) >> od) * 1000000;
|
|
}
|
|
|
|
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
|
|
{
|
|
ulong rate;
|
|
|
|
switch (id) {
|
|
case CLKID_FIXED_PLL:
|
|
case CLKID_SYS_PLL:
|
|
rate = meson_pll_get_rate(clk, id);
|
|
break;
|
|
case CLKID_FCLK_DIV2:
|
|
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
|
|
break;
|
|
case CLKID_FCLK_DIV3:
|
|
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
|
|
break;
|
|
case CLKID_FCLK_DIV4:
|
|
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
|
|
break;
|
|
case CLKID_FCLK_DIV5:
|
|
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
|
|
break;
|
|
case CLKID_FCLK_DIV7:
|
|
rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
|
|
break;
|
|
case CLKID_MPLL0:
|
|
case CLKID_MPLL1:
|
|
case CLKID_MPLL2:
|
|
rate = meson_mpll_get_rate(clk, id);
|
|
break;
|
|
case CLKID_CLK81:
|
|
rate = meson_clk81_get_rate(clk);
|
|
break;
|
|
case CLKID_VPU_0:
|
|
rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
|
|
break;
|
|
case CLKID_VPU_1:
|
|
rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
|
|
break;
|
|
case CLKID_VAPB:
|
|
rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
|
|
break;
|
|
case CLKID_VAPB_0:
|
|
rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
|
|
break;
|
|
case CLKID_VAPB_1:
|
|
rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
|
|
break;
|
|
case CLKID_VPU_0_DIV:
|
|
case CLKID_VPU_1_DIV:
|
|
case CLKID_VAPB_0_DIV:
|
|
case CLKID_VAPB_1_DIV:
|
|
rate = meson_div_get_rate(clk, id);
|
|
break;
|
|
case CLKID_VPU:
|
|
case CLKID_VPU_0_SEL:
|
|
case CLKID_VPU_1_SEL:
|
|
case CLKID_VAPB_SEL:
|
|
case CLKID_VAPB_0_SEL:
|
|
case CLKID_VAPB_1_SEL:
|
|
rate = meson_mux_get_rate(clk, id);
|
|
break;
|
|
default:
|
|
if (gates[id].reg != 0) {
|
|
/* a clock gate */
|
|
rate = meson_clk81_get_rate(clk);
|
|
break;
|
|
}
|
|
return -ENOENT;
|
|
}
|
|
|
|
debug("clock %lu has rate %lu\n", id, rate);
|
|
return rate;
|
|
}
|
|
|
|
static ulong meson_clk_get_rate(struct clk *clk)
|
|
{
|
|
return meson_clk_get_rate_by_id(clk, clk->id);
|
|
}
|
|
|
|
static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
return meson_mux_set_parent(clk, clk->id, parent->id);
|
|
}
|
|
|
|
static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
|
|
ulong rate, ulong current_rate)
|
|
{
|
|
if (current_rate == rate)
|
|
return 0;
|
|
|
|
switch (id) {
|
|
/* Fixed clocks */
|
|
case CLKID_FIXED_PLL:
|
|
case CLKID_SYS_PLL:
|
|
case CLKID_FCLK_DIV2:
|
|
case CLKID_FCLK_DIV3:
|
|
case CLKID_FCLK_DIV4:
|
|
case CLKID_FCLK_DIV5:
|
|
case CLKID_FCLK_DIV7:
|
|
case CLKID_MPLL0:
|
|
case CLKID_MPLL1:
|
|
case CLKID_MPLL2:
|
|
case CLKID_CLK81:
|
|
return -EINVAL;
|
|
case CLKID_VPU:
|
|
return meson_clk_set_rate_by_id(clk,
|
|
meson_mux_get_parent(clk, CLKID_VPU), rate,
|
|
current_rate);
|
|
case CLKID_VAPB:
|
|
case CLKID_VAPB_SEL:
|
|
return meson_clk_set_rate_by_id(clk,
|
|
meson_mux_get_parent(clk, CLKID_VAPB_SEL),
|
|
rate, current_rate);
|
|
case CLKID_VPU_0:
|
|
return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
|
|
current_rate);
|
|
case CLKID_VPU_1:
|
|
return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
|
|
current_rate);
|
|
case CLKID_VAPB_0:
|
|
return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
|
|
current_rate);
|
|
case CLKID_VAPB_1:
|
|
return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
|
|
current_rate);
|
|
case CLKID_VPU_0_DIV:
|
|
case CLKID_VPU_1_DIV:
|
|
case CLKID_VAPB_0_DIV:
|
|
case CLKID_VAPB_1_DIV:
|
|
return meson_div_set_rate(clk, id, rate, current_rate);
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
|
|
int ret;
|
|
|
|
if (IS_ERR_VALUE(current_rate))
|
|
return current_rate;
|
|
|
|
debug("%s: setting rate of %ld from %ld to %ld\n",
|
|
__func__, clk->id, current_rate, rate);
|
|
|
|
ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
|
|
if (IS_ERR_VALUE(ret))
|
|
return ret;
|
|
|
|
debug("clock %lu has new rate %lu\n", clk->id,
|
|
meson_clk_get_rate_by_id(clk, clk->id));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_clk_probe(struct udevice *dev)
|
|
{
|
|
struct meson_clk *priv = dev_get_priv(dev);
|
|
|
|
priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
|
|
if (IS_ERR(priv->map))
|
|
return PTR_ERR(priv->map);
|
|
|
|
/*
|
|
* Depending on the boot src, the state of the MMC clock might
|
|
* be different. Reset it to make sure we won't get stuck
|
|
*/
|
|
regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
|
|
regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
|
|
|
|
debug("meson-clk: probed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops meson_clk_ops = {
|
|
.disable = meson_clk_disable,
|
|
.enable = meson_clk_enable,
|
|
.get_rate = meson_clk_get_rate,
|
|
.set_parent = meson_clk_set_parent,
|
|
.set_rate = meson_clk_set_rate,
|
|
};
|
|
|
|
static const struct udevice_id meson_clk_ids[] = {
|
|
{ .compatible = "amlogic,gxbb-clkc" },
|
|
{ .compatible = "amlogic,gxl-clkc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(meson_clk) = {
|
|
.name = "meson_clk",
|
|
.id = UCLASS_CLK,
|
|
.of_match = meson_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct meson_clk),
|
|
.ops = &meson_clk_ops,
|
|
.probe = meson_clk_probe,
|
|
};
|