1051 lines
27 KiB
C
1051 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) STMicroelectronics 2019
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* Author: Christophe Kerello <christophe.kerello@st.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <nand.h>
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#include <reset.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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/* Bad block marker length */
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#define FMC2_BBM_LEN 2
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/* ECC step size */
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#define FMC2_ECC_STEP_SIZE 512
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/* Command delay */
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#define FMC2_RB_DELAY_US 30
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/* Max chip enable */
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#define FMC2_MAX_CE 2
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/* Timings */
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#define FMC2_THIZ 1
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#define FMC2_TIO 8000
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#define FMC2_TSYNC 3000
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#define FMC2_PCR_TIMING_MASK 0xf
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#define FMC2_PMEM_PATT_TIMING_MASK 0xff
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/* FMC2 Controller Registers */
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#define FMC2_BCR1 0x0
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#define FMC2_PCR 0x80
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#define FMC2_SR 0x84
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#define FMC2_PMEM 0x88
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#define FMC2_PATT 0x8c
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#define FMC2_HECCR 0x94
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#define FMC2_BCHISR 0x254
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#define FMC2_BCHICR 0x258
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#define FMC2_BCHPBR1 0x260
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#define FMC2_BCHPBR2 0x264
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#define FMC2_BCHPBR3 0x268
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#define FMC2_BCHPBR4 0x26c
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#define FMC2_BCHDSR0 0x27c
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#define FMC2_BCHDSR1 0x280
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#define FMC2_BCHDSR2 0x284
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#define FMC2_BCHDSR3 0x288
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#define FMC2_BCHDSR4 0x28c
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/* Register: FMC2_BCR1 */
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#define FMC2_BCR1_FMC2EN BIT(31)
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/* Register: FMC2_PCR */
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#define FMC2_PCR_PWAITEN BIT(1)
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#define FMC2_PCR_PBKEN BIT(2)
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#define FMC2_PCR_PWID GENMASK(5, 4)
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#define FMC2_PCR_PWID_BUSWIDTH_8 0
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#define FMC2_PCR_PWID_BUSWIDTH_16 1
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#define FMC2_PCR_ECCEN BIT(6)
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#define FMC2_PCR_ECCALG BIT(8)
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#define FMC2_PCR_TCLR GENMASK(12, 9)
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#define FMC2_PCR_TCLR_DEFAULT 0xf
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#define FMC2_PCR_TAR GENMASK(16, 13)
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#define FMC2_PCR_TAR_DEFAULT 0xf
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#define FMC2_PCR_ECCSS GENMASK(19, 17)
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#define FMC2_PCR_ECCSS_512 1
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#define FMC2_PCR_ECCSS_2048 3
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#define FMC2_PCR_BCHECC BIT(24)
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#define FMC2_PCR_WEN BIT(25)
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/* Register: FMC2_SR */
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#define FMC2_SR_NWRF BIT(6)
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/* Register: FMC2_PMEM */
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#define FMC2_PMEM_MEMSET GENMASK(7, 0)
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#define FMC2_PMEM_MEMWAIT GENMASK(15, 8)
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#define FMC2_PMEM_MEMHOLD GENMASK(23, 16)
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#define FMC2_PMEM_MEMHIZ GENMASK(31, 24)
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#define FMC2_PMEM_DEFAULT 0x0a0a0a0a
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/* Register: FMC2_PATT */
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#define FMC2_PATT_ATTSET GENMASK(7, 0)
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#define FMC2_PATT_ATTWAIT GENMASK(15, 8)
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#define FMC2_PATT_ATTHOLD GENMASK(23, 16)
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#define FMC2_PATT_ATTHIZ GENMASK(31, 24)
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#define FMC2_PATT_DEFAULT 0x0a0a0a0a
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/* Register: FMC2_BCHISR */
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#define FMC2_BCHISR_DERF BIT(1)
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#define FMC2_BCHISR_EPBRF BIT(4)
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/* Register: FMC2_BCHICR */
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#define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)
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/* Register: FMC2_BCHDSR0 */
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#define FMC2_BCHDSR0_DUE BIT(0)
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#define FMC2_BCHDSR0_DEF BIT(1)
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#define FMC2_BCHDSR0_DEN GENMASK(7, 4)
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/* Register: FMC2_BCHDSR1 */
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#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0)
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#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16)
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/* Register: FMC2_BCHDSR2 */
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#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0)
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#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16)
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/* Register: FMC2_BCHDSR3 */
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#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0)
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#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16)
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/* Register: FMC2_BCHDSR4 */
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#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
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#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
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#define FMC2_NSEC_PER_SEC 1000000000L
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#define FMC2_TIMEOUT_5S 5000000
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enum stm32_fmc2_ecc {
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FMC2_ECC_HAM = 1,
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FMC2_ECC_BCH4 = 4,
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FMC2_ECC_BCH8 = 8
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};
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struct stm32_fmc2_timings {
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u8 tclr;
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u8 tar;
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u8 thiz;
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u8 twait;
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u8 thold_mem;
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u8 tset_mem;
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u8 thold_att;
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u8 tset_att;
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};
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struct stm32_fmc2_nand {
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struct nand_chip chip;
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struct stm32_fmc2_timings timings;
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int ncs;
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int cs_used[FMC2_MAX_CE];
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};
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static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
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{
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return container_of(chip, struct stm32_fmc2_nand, chip);
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}
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struct stm32_fmc2_nfc {
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struct nand_hw_control base;
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struct stm32_fmc2_nand nand;
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struct nand_ecclayout ecclayout;
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fdt_addr_t io_base;
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fdt_addr_t data_base[FMC2_MAX_CE];
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fdt_addr_t cmd_base[FMC2_MAX_CE];
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fdt_addr_t addr_base[FMC2_MAX_CE];
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struct clk clk;
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u8 cs_assigned;
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int cs_sel;
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};
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static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
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{
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return container_of(base, struct stm32_fmc2_nfc, base);
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}
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static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
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struct stm32_fmc2_timings *timings = &nand->timings;
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u32 pmem, patt;
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/* Set tclr/tar timings */
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clrsetbits_le32(nfc->io_base + FMC2_PCR,
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FMC2_PCR_TCLR | FMC2_PCR_TAR,
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FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
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FIELD_PREP(FMC2_PCR_TAR, timings->tar));
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/* Set tset/twait/thold/thiz timings in common bank */
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pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
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pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
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pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
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pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
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writel(pmem, nfc->io_base + FMC2_PMEM);
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/* Set tset/twait/thold/thiz timings in attribut bank */
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patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
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patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
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patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
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patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
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writel(patt, nfc->io_base + FMC2_PATT);
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}
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static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 pcr = 0, pcr_mask;
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/* Configure ECC algorithm (default configuration is Hamming) */
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pcr_mask = FMC2_PCR_ECCALG;
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pcr_mask |= FMC2_PCR_BCHECC;
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if (chip->ecc.strength == FMC2_ECC_BCH8) {
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pcr |= FMC2_PCR_ECCALG;
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pcr |= FMC2_PCR_BCHECC;
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} else if (chip->ecc.strength == FMC2_ECC_BCH4) {
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pcr |= FMC2_PCR_ECCALG;
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}
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/* Set buswidth */
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pcr_mask |= FMC2_PCR_PWID;
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if (chip->options & NAND_BUSWIDTH_16)
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pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
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/* Set ECC sector size */
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pcr_mask |= FMC2_PCR_ECCSS;
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pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
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clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr);
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}
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static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
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if (chipnr < 0 || chipnr >= nand->ncs)
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return;
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if (nand->cs_used[chipnr] == nfc->cs_sel)
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return;
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nfc->cs_sel = nand->cs_used[chipnr];
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chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel];
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chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel];
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stm32_fmc2_nfc_setup(chip);
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stm32_fmc2_nfc_timings_init(chip);
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}
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static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc,
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bool set)
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{
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u32 pcr;
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pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
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FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
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clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr);
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}
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static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
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{
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clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN,
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enable ? FMC2_PCR_ECCEN : 0);
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}
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static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
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{
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writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR);
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}
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static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE) {
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writeb(cmd, nfc->cmd_base[nfc->cs_sel]);
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return;
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}
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writeb(cmd, nfc->addr_base[nfc->cs_sel]);
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}
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/*
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* Enable ECC logic and reset syndrome/parity bits previously calculated
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* Syndrome/parity bits is cleared by setting the ECCEN bit to 0
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*/
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static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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stm32_fmc2_nfc_set_ecc(nfc, false);
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if (chip->ecc.strength != FMC2_ECC_HAM) {
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clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN,
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mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
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stm32_fmc2_nfc_clear_bch_irq(nfc);
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}
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stm32_fmc2_nfc_set_ecc(nfc, true);
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}
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/*
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* ECC Hamming calculation
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* ECC is 3 bytes for 512 bytes of data (supports error correction up to
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* max of 1-bit)
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*/
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static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data,
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u8 *ecc)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 heccr, sr;
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int ret;
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ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
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sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
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if (ret < 0) {
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pr_err("Ham timeout\n");
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return ret;
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}
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heccr = readl(nfc->io_base + FMC2_HECCR);
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ecc[0] = heccr;
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ecc[1] = heccr >> 8;
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ecc[2] = heccr >> 16;
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stm32_fmc2_nfc_set_ecc(nfc, false);
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return 0;
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}
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static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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u8 bit_position = 0, b0, b1, b2;
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u32 byte_addr = 0, b;
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u32 i, shifting = 1;
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/* Indicate which bit and byte is faulty (if any) */
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b0 = read_ecc[0] ^ calc_ecc[0];
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b1 = read_ecc[1] ^ calc_ecc[1];
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b2 = read_ecc[2] ^ calc_ecc[2];
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b = b0 | (b1 << 8) | (b2 << 16);
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/* No errors */
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if (likely(!b))
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return 0;
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/* Calculate bit position */
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for (i = 0; i < 3; i++) {
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switch (b % 4) {
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case 2:
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bit_position += shifting;
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case 1:
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break;
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default:
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return -EBADMSG;
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}
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shifting <<= 1;
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b >>= 2;
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}
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/* Calculate byte position */
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shifting = 1;
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for (i = 0; i < 9; i++) {
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switch (b % 4) {
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case 2:
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byte_addr += shifting;
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case 1:
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break;
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default:
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return -EBADMSG;
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}
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shifting <<= 1;
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b >>= 2;
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}
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/* Flip the bit */
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dat[byte_addr] ^= (1 << bit_position);
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return 1;
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}
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/*
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* ECC BCH calculation and correction
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* ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
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* max of 4-bit/8-bit)
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*/
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static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data,
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u8 *ecc)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
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u32 bchpbr, bchisr;
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int ret;
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/* Wait until the BCH code is ready */
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ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
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bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
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if (ret < 0) {
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pr_err("Bch timeout\n");
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return ret;
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}
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/* Read parity bits */
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR1);
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ecc[0] = bchpbr;
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ecc[1] = bchpbr >> 8;
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ecc[2] = bchpbr >> 16;
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ecc[3] = bchpbr >> 24;
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR2);
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ecc[4] = bchpbr;
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ecc[5] = bchpbr >> 8;
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ecc[6] = bchpbr >> 16;
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if (chip->ecc.strength == FMC2_ECC_BCH8) {
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ecc[7] = bchpbr >> 24;
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR3);
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ecc[8] = bchpbr;
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ecc[9] = bchpbr >> 8;
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ecc[10] = bchpbr >> 16;
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ecc[11] = bchpbr >> 24;
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bchpbr = readl(nfc->io_base + FMC2_BCHPBR4);
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ecc[12] = bchpbr;
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}
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stm32_fmc2_nfc_set_ecc(nfc, false);
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return 0;
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}
|
|
|
|
static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat,
|
|
u8 *read_ecc, u8 *calc_ecc)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
|
|
u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
|
|
u16 pos[8];
|
|
int i, ret, den, eccsize = chip->ecc.size;
|
|
unsigned int nb_errs = 0;
|
|
|
|
/* Wait until the decoding error is ready */
|
|
ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
|
|
bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
|
|
if (ret < 0) {
|
|
pr_err("Bch timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0);
|
|
bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1);
|
|
bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2);
|
|
bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3);
|
|
bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4);
|
|
|
|
stm32_fmc2_nfc_set_ecc(nfc, false);
|
|
|
|
/* No errors found */
|
|
if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
|
|
return 0;
|
|
|
|
/* Too many errors detected */
|
|
if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
|
|
return -EBADMSG;
|
|
|
|
pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
|
|
pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
|
|
pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
|
|
pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
|
|
pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
|
|
pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
|
|
pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
|
|
pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
|
|
|
|
den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
|
|
for (i = 0; i < den; i++) {
|
|
if (pos[i] < eccsize * 8) {
|
|
__change_bit(pos[i], (unsigned long *)dat);
|
|
nb_errs++;
|
|
}
|
|
}
|
|
|
|
return nb_errs;
|
|
}
|
|
|
|
static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip, u8 *buf,
|
|
int oob_required, int page)
|
|
{
|
|
int i, s, stat, eccsize = chip->ecc.size;
|
|
int eccbytes = chip->ecc.bytes;
|
|
int eccsteps = chip->ecc.steps;
|
|
int eccstrength = chip->ecc.strength;
|
|
u8 *p = buf;
|
|
u8 *ecc_calc = chip->buffers->ecccalc;
|
|
u8 *ecc_code = chip->buffers->ecccode;
|
|
unsigned int max_bitflips = 0;
|
|
|
|
for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
|
|
s++, i += eccbytes, p += eccsize) {
|
|
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
|
|
|
/* Read the nand page sector (512 bytes) */
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
|
|
chip->read_buf(mtd, p, eccsize);
|
|
|
|
/* Read the corresponding ECC bytes */
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
|
|
chip->read_buf(mtd, ecc_code, eccbytes);
|
|
|
|
/* Correct the data */
|
|
stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
|
|
if (stat == -EBADMSG)
|
|
/* Check for empty pages with bitflips */
|
|
stat = nand_check_erased_ecc_chunk(p, eccsize,
|
|
ecc_code, eccbytes,
|
|
NULL, 0,
|
|
eccstrength);
|
|
|
|
if (stat < 0) {
|
|
mtd->ecc_stats.failed++;
|
|
} else {
|
|
mtd->ecc_stats.corrected += stat;
|
|
max_bitflips = max_t(unsigned int, max_bitflips, stat);
|
|
}
|
|
}
|
|
|
|
/* Read oob */
|
|
if (oob_required) {
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
|
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
}
|
|
|
|
return max_bitflips;
|
|
}
|
|
|
|
static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent)
|
|
{
|
|
u32 pcr = readl(nfc->io_base + FMC2_PCR);
|
|
|
|
/* Set CS used to undefined */
|
|
nfc->cs_sel = -1;
|
|
|
|
/* Enable wait feature and nand flash memory bank */
|
|
pcr |= FMC2_PCR_PWAITEN;
|
|
pcr |= FMC2_PCR_PBKEN;
|
|
|
|
/* Set buswidth to 8 bits mode for identification */
|
|
pcr &= ~FMC2_PCR_PWID;
|
|
|
|
/* ECC logic is disabled */
|
|
pcr &= ~FMC2_PCR_ECCEN;
|
|
|
|
/* Default mode */
|
|
pcr &= ~FMC2_PCR_ECCALG;
|
|
pcr &= ~FMC2_PCR_BCHECC;
|
|
pcr &= ~FMC2_PCR_WEN;
|
|
|
|
/* Set default ECC sector size */
|
|
pcr &= ~FMC2_PCR_ECCSS;
|
|
pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
|
|
|
|
/* Set default tclr/tar timings */
|
|
pcr &= ~FMC2_PCR_TCLR;
|
|
pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
|
|
pcr &= ~FMC2_PCR_TAR;
|
|
pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
|
|
|
|
/* Enable FMC2 controller */
|
|
if (!has_parent)
|
|
setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN);
|
|
|
|
writel(pcr, nfc->io_base + FMC2_PCR);
|
|
writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM);
|
|
writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT);
|
|
}
|
|
|
|
static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
|
|
const struct nand_sdr_timings *sdrt)
|
|
{
|
|
struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
|
|
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
|
|
struct stm32_fmc2_timings *tims = &nand->timings;
|
|
unsigned long hclk = clk_get_rate(&nfc->clk);
|
|
unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
|
|
unsigned long timing, tar, tclr, thiz, twait;
|
|
unsigned long tset_mem, tset_att, thold_mem, thold_att;
|
|
|
|
tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
|
|
timing = DIV_ROUND_UP(tar, hclkp) - 1;
|
|
tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
|
|
|
|
tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
|
|
timing = DIV_ROUND_UP(tclr, hclkp) - 1;
|
|
tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
|
|
|
|
tims->thiz = FMC2_THIZ;
|
|
thiz = (tims->thiz + 1) * hclkp;
|
|
|
|
/*
|
|
* tWAIT > tRP
|
|
* tWAIT > tWP
|
|
* tWAIT > tREA + tIO
|
|
*/
|
|
twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
|
|
twait = max_t(unsigned long, twait, sdrt->tWP_min);
|
|
twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
|
|
timing = DIV_ROUND_UP(twait, hclkp);
|
|
tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
|
|
|
|
/*
|
|
* tSETUP_MEM > tCS - tWAIT
|
|
* tSETUP_MEM > tALS - tWAIT
|
|
* tSETUP_MEM > tDS - (tWAIT - tHIZ)
|
|
*/
|
|
tset_mem = hclkp;
|
|
if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
|
|
tset_mem = sdrt->tCS_min - twait;
|
|
if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
|
|
tset_mem = sdrt->tALS_min - twait;
|
|
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
|
|
(tset_mem < sdrt->tDS_min - (twait - thiz)))
|
|
tset_mem = sdrt->tDS_min - (twait - thiz);
|
|
timing = DIV_ROUND_UP(tset_mem, hclkp);
|
|
tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
|
|
|
|
/*
|
|
* tHOLD_MEM > tCH
|
|
* tHOLD_MEM > tREH - tSETUP_MEM
|
|
* tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
|
|
*/
|
|
thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
|
|
if (sdrt->tREH_min > tset_mem &&
|
|
(thold_mem < sdrt->tREH_min - tset_mem))
|
|
thold_mem = sdrt->tREH_min - tset_mem;
|
|
if ((sdrt->tRC_min > tset_mem + twait) &&
|
|
(thold_mem < sdrt->tRC_min - (tset_mem + twait)))
|
|
thold_mem = sdrt->tRC_min - (tset_mem + twait);
|
|
if ((sdrt->tWC_min > tset_mem + twait) &&
|
|
(thold_mem < sdrt->tWC_min - (tset_mem + twait)))
|
|
thold_mem = sdrt->tWC_min - (tset_mem + twait);
|
|
timing = DIV_ROUND_UP(thold_mem, hclkp);
|
|
tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
|
|
|
|
/*
|
|
* tSETUP_ATT > tCS - tWAIT
|
|
* tSETUP_ATT > tCLS - tWAIT
|
|
* tSETUP_ATT > tALS - tWAIT
|
|
* tSETUP_ATT > tRHW - tHOLD_MEM
|
|
* tSETUP_ATT > tDS - (tWAIT - tHIZ)
|
|
*/
|
|
tset_att = hclkp;
|
|
if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
|
|
tset_att = sdrt->tCS_min - twait;
|
|
if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
|
|
tset_att = sdrt->tCLS_min - twait;
|
|
if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
|
|
tset_att = sdrt->tALS_min - twait;
|
|
if (sdrt->tRHW_min > thold_mem &&
|
|
(tset_att < sdrt->tRHW_min - thold_mem))
|
|
tset_att = sdrt->tRHW_min - thold_mem;
|
|
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
|
|
(tset_att < sdrt->tDS_min - (twait - thiz)))
|
|
tset_att = sdrt->tDS_min - (twait - thiz);
|
|
timing = DIV_ROUND_UP(tset_att, hclkp);
|
|
tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
|
|
|
|
/*
|
|
* tHOLD_ATT > tALH
|
|
* tHOLD_ATT > tCH
|
|
* tHOLD_ATT > tCLH
|
|
* tHOLD_ATT > tCOH
|
|
* tHOLD_ATT > tDH
|
|
* tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
|
|
* tHOLD_ATT > tADL - tSETUP_MEM
|
|
* tHOLD_ATT > tWH - tSETUP_MEM
|
|
* tHOLD_ATT > tWHR - tSETUP_MEM
|
|
* tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
|
|
* tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
|
|
*/
|
|
thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
|
|
thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
|
|
thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
|
|
thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
|
|
thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
|
|
if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
|
|
(thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
|
|
thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
|
|
if (sdrt->tADL_min > tset_mem &&
|
|
(thold_att < sdrt->tADL_min - tset_mem))
|
|
thold_att = sdrt->tADL_min - tset_mem;
|
|
if (sdrt->tWH_min > tset_mem &&
|
|
(thold_att < sdrt->tWH_min - tset_mem))
|
|
thold_att = sdrt->tWH_min - tset_mem;
|
|
if (sdrt->tWHR_min > tset_mem &&
|
|
(thold_att < sdrt->tWHR_min - tset_mem))
|
|
thold_att = sdrt->tWHR_min - tset_mem;
|
|
if ((sdrt->tRC_min > tset_att + twait) &&
|
|
(thold_att < sdrt->tRC_min - (tset_att + twait)))
|
|
thold_att = sdrt->tRC_min - (tset_att + twait);
|
|
if ((sdrt->tWC_min > tset_att + twait) &&
|
|
(thold_att < sdrt->tWC_min - (tset_att + twait)))
|
|
thold_att = sdrt->tWC_min - (tset_att + twait);
|
|
timing = DIV_ROUND_UP(thold_att, hclkp);
|
|
tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
|
|
}
|
|
|
|
static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr,
|
|
const struct nand_data_interface *cf)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
const struct nand_sdr_timings *sdrt;
|
|
|
|
sdrt = nand_get_sdr_timings(cf);
|
|
if (IS_ERR(sdrt))
|
|
return PTR_ERR(sdrt);
|
|
|
|
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
|
|
return 0;
|
|
|
|
stm32_fmc2_nfc_calc_timings(chip, sdrt);
|
|
stm32_fmc2_nfc_timings_init(chip);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
|
|
{
|
|
chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
|
|
|
|
/*
|
|
* Specific callbacks to read/write a page depending on
|
|
* the algo used (Hamming, BCH).
|
|
*/
|
|
if (chip->ecc.strength == FMC2_ECC_HAM) {
|
|
/* Hamming is used */
|
|
chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
|
|
chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
|
|
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
|
|
chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
|
|
return;
|
|
}
|
|
|
|
/* BCH is used */
|
|
chip->ecc.read_page = stm32_fmc2_nfc_read_page;
|
|
chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
|
|
chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
|
|
|
|
if (chip->ecc.strength == FMC2_ECC_BCH8)
|
|
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
|
|
else
|
|
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
|
|
}
|
|
|
|
static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
|
|
{
|
|
/* Hamming */
|
|
if (strength == FMC2_ECC_HAM)
|
|
return 4;
|
|
|
|
/* BCH8 */
|
|
if (strength == FMC2_ECC_BCH8)
|
|
return 14;
|
|
|
|
/* BCH4 */
|
|
return 8;
|
|
}
|
|
|
|
NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
|
|
FMC2_ECC_STEP_SIZE,
|
|
FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
|
|
|
|
static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node)
|
|
{
|
|
struct stm32_fmc2_nand *nand = &nfc->nand;
|
|
u32 cs[FMC2_MAX_CE];
|
|
int ret, i;
|
|
|
|
if (!ofnode_get_property(node, "reg", &nand->ncs))
|
|
return -EINVAL;
|
|
|
|
nand->ncs /= sizeof(u32);
|
|
if (!nand->ncs) {
|
|
pr_err("Invalid reg property size\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
|
|
if (ret < 0) {
|
|
pr_err("Could not retrieve reg property\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < nand->ncs; i++) {
|
|
if (cs[i] >= FMC2_MAX_CE) {
|
|
pr_err("Invalid reg value: %d\n",
|
|
nand->cs_used[i]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (nfc->cs_assigned & BIT(cs[i])) {
|
|
pr_err("Cs already assigned: %d\n",
|
|
nand->cs_used[i]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
nfc->cs_assigned |= BIT(cs[i]);
|
|
nand->cs_used[i] = cs[i];
|
|
}
|
|
|
|
nand->chip.flash_node = ofnode_to_offset(node);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_fmc2_nfc_parse_dt(struct udevice *dev,
|
|
struct stm32_fmc2_nfc *nfc)
|
|
{
|
|
ofnode child;
|
|
int ret, nchips = 0;
|
|
|
|
dev_for_each_subnode(child, dev)
|
|
nchips++;
|
|
|
|
if (!nchips) {
|
|
pr_err("NAND chip not defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (nchips > 1) {
|
|
pr_err("Too many NAND chips defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dev_for_each_subnode(child, dev) {
|
|
ret = stm32_fmc2_nfc_parse_child(nfc, child);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev)
|
|
{
|
|
struct udevice *pdev = dev_get_parent(dev);
|
|
struct udevice *cdev = NULL;
|
|
bool ebi_found = false;
|
|
|
|
if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev),
|
|
"st,stm32mp1-fmc2-ebi"))
|
|
ebi_found = true;
|
|
|
|
if (ofnode_device_is_compatible(dev_ofnode(dev),
|
|
"st,stm32mp1-fmc2-nfc")) {
|
|
if (ebi_found)
|
|
cdev = pdev;
|
|
|
|
return cdev;
|
|
}
|
|
|
|
if (!ebi_found)
|
|
cdev = dev;
|
|
|
|
return cdev;
|
|
}
|
|
|
|
static int stm32_fmc2_nfc_probe(struct udevice *dev)
|
|
{
|
|
struct stm32_fmc2_nfc *nfc = dev_get_priv(dev);
|
|
struct stm32_fmc2_nand *nand = &nfc->nand;
|
|
struct nand_chip *chip = &nand->chip;
|
|
struct mtd_info *mtd = &chip->mtd;
|
|
struct nand_ecclayout *ecclayout;
|
|
struct udevice *cdev;
|
|
struct reset_ctl reset;
|
|
int oob_index, chip_cs, mem_region, ret;
|
|
unsigned int i;
|
|
int start_region = 0;
|
|
fdt_addr_t addr;
|
|
|
|
spin_lock_init(&nfc->controller.lock);
|
|
init_waitqueue_head(&nfc->controller.wq);
|
|
|
|
cdev = stm32_fmc2_nfc_get_cdev(dev);
|
|
if (!cdev)
|
|
return -EINVAL;
|
|
|
|
ret = stm32_fmc2_nfc_parse_dt(dev, nfc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nfc->io_base = dev_read_addr(cdev);
|
|
if (nfc->io_base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
if (dev == cdev)
|
|
start_region = 1;
|
|
|
|
for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
|
|
chip_cs++, mem_region += 3) {
|
|
if (!(nfc->cs_assigned & BIT(chip_cs)))
|
|
continue;
|
|
|
|
addr = dev_read_addr_index(dev, mem_region);
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
pr_err("Resource data_base not found for cs%d",
|
|
chip_cs);
|
|
return ret;
|
|
}
|
|
nfc->data_base[chip_cs] = addr;
|
|
|
|
addr = dev_read_addr_index(dev, mem_region + 1);
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
pr_err("Resource cmd_base not found for cs%d",
|
|
chip_cs);
|
|
return ret;
|
|
}
|
|
nfc->cmd_base[chip_cs] = addr;
|
|
|
|
addr = dev_read_addr_index(dev, mem_region + 2);
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
pr_err("Resource addr_base not found for cs%d",
|
|
chip_cs);
|
|
return ret;
|
|
}
|
|
nfc->addr_base[chip_cs] = addr;
|
|
}
|
|
|
|
/* Enable the clock */
|
|
ret = clk_get_by_index(cdev, 0, &nfc->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_enable(&nfc->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Reset */
|
|
ret = reset_get_by_index(dev, 0, &reset);
|
|
if (!ret) {
|
|
reset_assert(&reset);
|
|
udelay(2);
|
|
reset_deassert(&reset);
|
|
}
|
|
|
|
stm32_fmc2_nfc_init(nfc, dev != cdev);
|
|
|
|
chip->controller = &nfc->base;
|
|
chip->select_chip = stm32_fmc2_nfc_select_chip;
|
|
chip->setup_data_interface = stm32_fmc2_nfc_setup_interface;
|
|
chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl;
|
|
chip->chip_delay = FMC2_RB_DELAY_US;
|
|
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
|
|
NAND_USE_BOUNCE_BUFFER;
|
|
|
|
/* Default ECC settings */
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
chip->ecc.size = FMC2_ECC_STEP_SIZE;
|
|
chip->ecc.strength = FMC2_ECC_BCH8;
|
|
|
|
ret = nand_scan_ident(mtd, nand->ncs, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Only NAND_ECC_HW mode is actually supported
|
|
* Hamming => ecc.strength = 1
|
|
* BCH4 => ecc.strength = 4
|
|
* BCH8 => ecc.strength = 8
|
|
* ECC sector size = 512
|
|
*/
|
|
if (chip->ecc.mode != NAND_ECC_HW) {
|
|
pr_err("Nand_ecc_mode is not well defined in the DT\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
|
|
mtd->oobsize - FMC2_BBM_LEN);
|
|
if (ret) {
|
|
pr_err("No valid ECC settings set\n");
|
|
return ret;
|
|
}
|
|
|
|
if (chip->bbt_options & NAND_BBT_USE_FLASH)
|
|
chip->bbt_options |= NAND_BBT_NO_OOB;
|
|
|
|
stm32_fmc2_nfc_nand_callbacks_setup(chip);
|
|
|
|
/* Define ECC layout */
|
|
ecclayout = &nfc->ecclayout;
|
|
ecclayout->eccbytes = chip->ecc.bytes *
|
|
(mtd->writesize / chip->ecc.size);
|
|
oob_index = FMC2_BBM_LEN;
|
|
for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
|
|
ecclayout->eccpos[i] = oob_index;
|
|
ecclayout->oobfree->offset = oob_index;
|
|
ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
|
|
chip->ecc.layout = ecclayout;
|
|
|
|
if (chip->options & NAND_BUSWIDTH_16)
|
|
stm32_fmc2_nfc_set_buswidth_16(nfc, true);
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return nand_register(0, mtd);
|
|
}
|
|
|
|
static const struct udevice_id stm32_fmc2_nfc_match[] = {
|
|
{ .compatible = "st,stm32mp15-fmc2" },
|
|
{ .compatible = "st,stm32mp1-fmc2-nfc" },
|
|
{ /* Sentinel */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32_fmc2_nfc) = {
|
|
.name = "stm32_fmc2_nfc",
|
|
.id = UCLASS_MTD,
|
|
.of_match = stm32_fmc2_nfc_match,
|
|
.probe = stm32_fmc2_nfc_probe,
|
|
.priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
|
|
};
|
|
|
|
void board_nand_init(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
|
DM_GET_DRIVER(stm32_fmc2_nfc),
|
|
&dev);
|
|
if (ret && ret != -ENODEV)
|
|
pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
|
|
ret);
|
|
}
|