268 lines
6.4 KiB
C
268 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* OMAP USB PHY Support
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*/
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#include <common.h>
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#include <usb.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/omap_common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/compat.h>
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#include <linux/usb/dwc3.h>
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#include <linux/usb/xhci-omap.h>
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#include <usb/xhci.h>
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#ifdef CONFIG_OMAP_USB3PHY1_HOST
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struct usb3_dpll_params {
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u16 m;
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u8 n;
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u8 freq:3;
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u8 sd;
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u32 mf;
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};
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struct usb3_dpll_map {
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unsigned long rate;
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struct usb3_dpll_params params;
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struct usb3_dpll_map *dpll_map;
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};
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static struct usb3_dpll_map dpll_map_usb[] = {
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{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
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{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
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{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
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{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
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{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
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{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
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{ }, /* Terminator */
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};
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static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
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{
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unsigned long rate;
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struct usb3_dpll_map *dpll_map = dpll_map_usb;
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rate = get_sys_clk_freq();
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for (; dpll_map->rate; dpll_map++) {
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if (rate == dpll_map->rate)
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return &dpll_map->params;
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}
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dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
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return NULL;
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}
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static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
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{
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u32 val;
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writel(SET_PLL_GO, &phy_regs->pll_go);
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do {
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val = readl(&phy_regs->pll_status);
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if (val & PLL_LOCK)
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break;
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} while (1);
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}
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static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
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{
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struct usb3_dpll_params *dpll_params;
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u32 val;
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dpll_params = omap_usb3_get_dpll_params();
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if (!dpll_params)
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return;
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val = readl(&phy_regs->pll_config_1);
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val &= ~PLL_REGN_MASK;
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val |= dpll_params->n << PLL_REGN_SHIFT;
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writel(val, &phy_regs->pll_config_1);
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val = readl(&phy_regs->pll_config_2);
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val &= ~PLL_SELFREQDCO_MASK;
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
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writel(val, &phy_regs->pll_config_2);
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val = readl(&phy_regs->pll_config_1);
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val &= ~PLL_REGM_MASK;
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val |= dpll_params->m << PLL_REGM_SHIFT;
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writel(val, &phy_regs->pll_config_1);
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val = readl(&phy_regs->pll_config_4);
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val &= ~PLL_REGM_F_MASK;
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val |= dpll_params->mf << PLL_REGM_F_SHIFT;
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writel(val, &phy_regs->pll_config_4);
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val = readl(&phy_regs->pll_config_3);
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val &= ~PLL_SD_MASK;
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val |= dpll_params->sd << PLL_SD_SHIFT;
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writel(val, &phy_regs->pll_config_3);
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omap_usb_dpll_relock(phy_regs);
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}
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static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
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{
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u32 rate = get_sys_clk_freq()/1000000;
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u32 val;
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val = readl((*ctrl)->control_phy_power_usb);
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val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
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val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
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val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
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writel(val, (*ctrl)->control_phy_power_usb);
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}
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void usb_phy_power(int on)
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{
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u32 val;
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val = readl((*ctrl)->control_phy_power_usb);
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if (on) {
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val &= ~USB3_PWRCTL_CLK_CMD_MASK;
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val |= USB3_PHY_TX_RX_POWERON;
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} else {
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val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
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}
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writel(val, (*ctrl)->control_phy_power_usb);
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}
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void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
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{
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omap_usb_dpll_lock(phy_regs);
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usb3_phy_partial_powerup(phy_regs);
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/*
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* Give enough time for the PHY to partially power-up before
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* powering it up completely. delay value suggested by the HW
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* team.
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*/
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mdelay(100);
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}
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static void omap_enable_usb3_phy(struct omap_xhci *omap)
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{
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u32 val;
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val = (USBOTGSS_DMADISABLE |
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USBOTGSS_STANDBYMODE_SMRT_WKUP |
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USBOTGSS_IDLEMODE_NOIDLE);
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writel(val, &omap->otg_wrapper->sysconfig);
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/* Clear the utmi OTG status */
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val = readl(&omap->otg_wrapper->utmi_otg_status);
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writel(val, &omap->otg_wrapper->utmi_otg_status);
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/* Enable interrupts */
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writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
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val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
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USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
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USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
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USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
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USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
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USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
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USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
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USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
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USBOTGSS_IRQ_SET_1_OEVT_EN);
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writel(val, &omap->otg_wrapper->irqenable_set_1);
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/* Clear the IRQ status */
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val = readl(&omap->otg_wrapper->irqstatus_1);
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writel(val, &omap->otg_wrapper->irqstatus_1);
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val = readl(&omap->otg_wrapper->irqstatus_0);
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writel(val, &omap->otg_wrapper->irqstatus_0);
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};
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#endif /* CONFIG_OMAP_USB3PHY1_HOST */
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#ifdef CONFIG_OMAP_USB2PHY2_HOST
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static void omap_enable_usb2_phy2(struct omap_xhci *omap)
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{
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u32 reg, val;
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val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
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writel(val, (*ctrl)->control_srcomp_north_side);
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setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
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USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
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setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
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(USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
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OTG_SS_CLKCTRL_MODULEMODE_HW));
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/* This is an undocumented Reserved register */
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reg = 0x4a0086c0;
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val = readl(reg);
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val |= 0x100;
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setbits_le32(reg, val);
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}
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void usb_phy_power(int on)
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{
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return;
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}
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#endif /* CONFIG_OMAP_USB2PHY2_HOST */
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#ifdef CONFIG_AM437X_USB2PHY2_HOST
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static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
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{
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const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
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USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
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writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
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writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
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writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
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writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
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}
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void usb_phy_power(int on)
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{
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u32 val;
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/* USB1_CTRL */
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val = readl(USB1_CTRL);
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if (on) {
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/*
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* these bits are re-used on AM437x to power up/down the USB
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* CM and OTG PHYs, if we don't toggle them, USB will not be
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* functional on newer silicon revisions
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*/
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val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
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} else {
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val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
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}
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writel(val, USB1_CTRL);
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}
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#endif /* CONFIG_AM437X_USB2PHY2_HOST */
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void omap_enable_phy(struct omap_xhci *omap)
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{
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#ifdef CONFIG_OMAP_USB2PHY2_HOST
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omap_enable_usb2_phy2(omap);
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#endif
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#ifdef CONFIG_AM437X_USB2PHY2_HOST
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am437x_enable_usb2_phy2(omap);
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#endif
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#ifdef CONFIG_OMAP_USB3PHY1_HOST
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omap_enable_usb3_phy(omap);
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omap_usb3_phy_init(omap->usb3_phy);
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#endif
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}
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