145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sdram_bank {
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u32 win_bar;
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u32 win_sz;
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};
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struct sdram_addr_dec {
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struct sdram_bank sdram_bank[4];
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};
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#define REG_CPUCS_WIN_ENABLE (1 << 0)
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#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
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#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
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#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
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/*
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* mvebu_sdram_bar - reads SDRAM Base Address Register
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*/
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u32 mvebu_sdram_bar(enum memory_bank bank)
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{
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struct sdram_addr_dec *base =
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(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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return 0;
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result = readl(&base->sdram_bank[bank].win_bar);
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return result;
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}
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/*
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* mvebu_sdram_bs_set - writes SDRAM Bank size
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*/
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static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
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{
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struct sdram_addr_dec *base =
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(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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/* Read current register value */
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u32 reg = readl(&base->sdram_bank[bank].win_sz);
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/* Clear window size */
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reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
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/* Set new window size */
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reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
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writel(reg, &base->sdram_bank[bank].win_sz);
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}
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/*
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* mvebu_sdram_bs - reads SDRAM Bank size
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*/
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u32 mvebu_sdram_bs(enum memory_bank bank)
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{
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struct sdram_addr_dec *base =
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(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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return 0;
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result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
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result += 0x01000000;
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return result;
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}
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void mvebu_sdram_size_adjust(enum memory_bank bank)
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{
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u32 size;
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/* probe currently equipped RAM size */
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size = get_ram_size((void *)mvebu_sdram_bar(bank),
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mvebu_sdram_bs(bank));
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/* adjust SDRAM window size accordingly */
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mvebu_sdram_bs_set(bank, size);
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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int dram_init(void)
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{
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int i;
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gd->ram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
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gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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* If the gap is found, ram_size will be reported for
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* consecutive memory only
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*/
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if (gd->bd->bi_dram[i].start != gd->ram_size)
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break;
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/*
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* Don't report more than 3GiB of SDRAM, otherwise there is no
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* address space left for the internal registers etc.
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*/
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if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
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(gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
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gd->ram_size += gd->bd->bi_dram[i].size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* If above loop terminated prematurely, we need to set
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* remaining banks' start address & size as 0. Otherwise other
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* u-boot functions and Linux kernel gets wrong values which
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* could result in crash */
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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return 0;
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}
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/*
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* If this function is not defined here,
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* board.c alters dram bank zero configuration defined above.
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*/
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void dram_init_banksize(void)
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{
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dram_init();
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}
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#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
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