74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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#include <asm/sysreg.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include "hsmc3.h"
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/* Sanity checks */
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#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \
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|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \
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|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
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# error Constraint fCPU >= fHSB >= fPB{A,B} violated
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#endif
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#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
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# error Invalid PLL multiplier and/or divider
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int cpu_init(void)
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{
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extern void _evba(void);
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gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
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/* TODO: Move somewhere else, but needs to be run before we
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* increase the clock frequency. */
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hsmc3_writel(MODE0, 0x00031103);
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hsmc3_writel(CYCLE0, 0x000c000d);
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hsmc3_writel(PULSE0, 0x0b0a0906);
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hsmc3_writel(SETUP0, 0x00010002);
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clk_init();
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/* Update the CPU speed according to the PLL configuration */
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gd->arch.cpu_hz = get_cpu_clk_rate();
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/* Set up the exception handler table and enable exceptions */
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sysreg_write(EVBA, (unsigned long)&_evba);
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asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
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return 0;
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}
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void prepare_to_boot(void)
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{
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/* Flush both caches and the write buffer */
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asm volatile("cache %0[4], 010\n\t"
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"cache %0[0], 000\n\t"
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"sync 0" : : "r"(0) : "memory");
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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/* This will reset the CPU core, caches, MMU and all internal busses */
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__builtin_mtdr(8, 1 << 13); /* set DC:DBE */
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__builtin_mtdr(8, 1 << 30); /* set DC:RES */
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/* Flush the pipeline before we declare it a failure */
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asm volatile("sub pc, pc, -4");
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return -1;
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}
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