119 lines
3.4 KiB
C
119 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _RESET_MANAGER_S10_
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#define _RESET_MANAGER_S10_
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void reset_cpu(ulong addr);
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int cpu_has_been_warmreset(void);
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void socfpga_bridges_reset(int enable);
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void socfpga_per_reset(u32 reset, int set);
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void socfpga_per_reset_all(void);
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struct socfpga_reset_manager {
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u32 status;
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u32 mpu_rst_stat;
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u32 misc_stat;
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u32 padding1;
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u32 hdsk_en;
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u32 hdsk_req;
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u32 hdsk_ack;
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u32 hdsk_stall;
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u32 mpumodrst;
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u32 per0modrst;
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u32 per1modrst;
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u32 brgmodrst;
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u32 padding2;
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u32 cold_mod_reset;
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u32 padding3;
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u32 dbg_mod_reset;
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u32 tap_mod_reset;
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u32 padding4;
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u32 padding5;
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u32 brg_warm_mask;
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u32 padding6[3];
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u32 tst_stat;
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u32 padding7;
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u32 hdsk_timeout;
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u32 mpul2flushtimeout;
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u32 dbghdsktimeout;
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};
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#define RSTMGR_MPUMODRST_CORE0 0
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#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
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#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
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#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
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/* Watchdogs and MPU warm reset mask */
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#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
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/*
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* Define a reset identifier, from which a permodrst bank ID
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* and reset ID can be extracted using the subsequent macros
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* RSTMGR_RESET() and RSTMGR_BANK().
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*/
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#define RSTMGR_BANK_OFFSET 8
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#define RSTMGR_BANK_MASK 0x7
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#define RSTMGR_RESET_OFFSET 0
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#define RSTMGR_RESET_MASK 0x1f
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#define RSTMGR_DEFINE(_bank, _offset) \
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((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
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/* Extract reset ID from the reset identifier. */
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#define RSTMGR_RESET(_reset) \
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(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
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/* Extract bank ID from the reset identifier. */
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#define RSTMGR_BANK(_reset) \
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(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
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/*
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* SocFPGA Stratix10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
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#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
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#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
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#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
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#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
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#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
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#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
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#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
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#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
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#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
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#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
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#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
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#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
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#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
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#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
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#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
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#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
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#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
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#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
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#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
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#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
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/* Create a human-readable reference to SoCFPGA reset. */
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#define SOCFPGA_RESET(_name) RSTMGR_##_name
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#endif /* _RESET_MANAGER_S10_ */
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