790f7719e2
Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
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| .. | ||
| clock-tables.h | ||
| clock.h | ||
| flow.h | ||
| funcmux.h | ||
| gp_padctrl.h | ||
| gpio.h | ||
| hardware.h | ||
| mc.h | ||
| pinmux.h | ||
| pmu.h | ||
| powergate.h | ||
| sysctr.h | ||
| tegra.h | ||