101 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			101 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * (C) Copyright 2009
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|  * Marvell Semiconductor <www.marvell.com>
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|  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <asm/io.h>
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| #include <usb.h>
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| #include "ehci.h"
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| #include <asm/arch/cpu.h>
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| 
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| #if defined(CONFIG_KIRKWOOD)
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| #include <asm/arch/soc.h>
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| #elif defined(CONFIG_ORION5X)
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| #include <asm/arch/orion5x.h>
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| #endif
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| #define rdl(off)	readl(MVUSB0_BASE + (off))
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| #define wrl(off, val)	writel((val), MVUSB0_BASE + (off))
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| 
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| #define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
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| #define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
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| #define USB_TARGET_DRAM		0x0
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| 
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| /*
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|  * USB 2.0 Bridge Address Decoding registers setup
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|  */
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| static void usb_brg_adrdec_setup(void)
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| {
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| 	int i;
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| 	u32 size, base, attrib;
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| 
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| 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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| 
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| 		/* Enable DRAM bank */
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| 		switch (i) {
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| 		case 0:
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| 			attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
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| 			break;
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| 		case 1:
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| 			attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
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| 			break;
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| 		case 2:
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| 			attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
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| 			break;
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| 		case 3:
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| 			attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
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| 			break;
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| 		default:
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| 			/* invalide bank, disable access */
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| 			attrib = 0;
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| 			break;
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| 		}
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| 
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| 		size = gd->bd->bi_dram[i].size;
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| 		base = gd->bd->bi_dram[i].start;
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| 		if ((size) && (attrib))
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| 			wrl(USB_WINDOW_CTRL(i),
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| 				MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
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| 					attrib, MVCPU_WIN_ENABLE));
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| 		else
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| 			wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
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| 
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| 		wrl(USB_WINDOW_BASE(i), base);
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| 	}
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| }
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| 
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| /*
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|  * Create the appropriate control structures to manage
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|  * a new EHCI host controller.
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|  */
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| int ehci_hcd_init(int index, enum usb_init_type init,
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| 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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| {
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| 	usb_brg_adrdec_setup();
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| 
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| 	*hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
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| 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
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| 			+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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| 
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| 	debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
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| 		(uint32_t)*hccr, (uint32_t)*hcor,
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| 		(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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| 
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| 	return 0;
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| }
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| 
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| /*
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|  * Destroy the appropriate control structures corresponding
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|  * the the EHCI host controller.
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|  */
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| int ehci_hcd_stop(int index)
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| {
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| 	return 0;
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| }
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