124 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			124 lines
		
	
	
		
			3.3 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * Copyright 2010-2011 Freescale Semiconductor, Inc.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #ifndef __FSL_SECURE_BOOT_H
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| #define __FSL_SECURE_BOOT_H
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| #include <asm/config_mpc85xx.h>
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| 
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| #ifdef CONFIG_SECURE_BOOT
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| 
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| #ifndef CONFIG_FIT_SIGNATURE
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| #define CONFIG_CHAIN_OF_TRUST
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| #endif
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| 
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| #if defined(CONFIG_FSL_CORENET)
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| #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
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| #elif defined(CONFIG_BSC9132QDS)
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| #define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
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| #elif defined(CONFIG_C29XPCIE)
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| #define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
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| #else
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| #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
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| #endif
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| #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
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| 
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| #if defined(CONFIG_B4860QDS) || \
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| 	defined(CONFIG_T4240QDS) || \
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| 	defined(CONFIG_T2080QDS) || \
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| 	defined(CONFIG_T2080RDB) || \
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| 	defined(CONFIG_T1040QDS) || \
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| 	defined(CONFIG_T104xD4QDS) || \
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| 	defined(CONFIG_T104xRDB) || \
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| 	defined(CONFIG_T104xD4RDB) || \
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| 	defined(CONFIG_PPC_T1023) || \
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| 	defined(CONFIG_PPC_T1024)
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| #define CONFIG_SYS_CPC_REINIT_F
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| #define CONFIG_KEY_REVOCATION
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| #undef CONFIG_SYS_INIT_L3_ADDR
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| #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
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| #endif
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| 
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| #if defined(CONFIG_RAMBOOT_PBL)
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| #undef CONFIG_SYS_INIT_L3_ADDR
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| #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
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| #endif
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| 
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| #if defined(CONFIG_C29XPCIE)
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| #define CONFIG_KEY_REVOCATION
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| #endif
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| 
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| #if defined(CONFIG_PPC_P3041)	||	\
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| 	defined(CONFIG_PPC_P4080) ||	\
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| 	defined(CONFIG_PPC_P5020) ||	\
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| 	defined(CONFIG_PPC_P5040) ||	\
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| 	defined(CONFIG_PPC_P2041)
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| 	#define	CONFIG_FSL_TRUST_ARCH_v1
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| #endif
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| 
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| #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
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| /* The key used for verification of next level images
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|  * is picked up from an Extension Table which has
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|  * been verified by the ISBC (Internal Secure boot Code)
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|  * in boot ROM of the SoC.
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|  * The feature is only applicable in case of NOR boot and is
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|  * not applicable in case of RAMBOOT (NAND, SD, SPI).
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|  */
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| #define CONFIG_FSL_ISBC_KEY_EXT
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| #endif
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| #endif /* #ifdef CONFIG_SECURE_BOOT */
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| 
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| #ifdef CONFIG_CHAIN_OF_TRUST
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| 
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| #define CONFIG_CMD_ESBC_VALIDATE
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| #define CONFIG_CMD_BLOB
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| #define CONFIG_FSL_SEC_MON
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| #define CONFIG_SHA_PROG_HW_ACCEL
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| #define CONFIG_RSA_FREESCALE_EXP
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| 
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| #ifndef CONFIG_FSL_CAAM
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| #define CONFIG_FSL_CAAM
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| #endif
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| 
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| /* fsl_setenv_chain_of_trust() must be called from
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|  * board_late_init()
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|  */
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| #ifndef CONFIG_BOARD_LATE_INIT
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| #define CONFIG_BOARD_LATE_INIT
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| #endif
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| 
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| /* If Boot Script is not on NOR and is required to be copied on RAM */
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| #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
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| #define CONFIG_BS_HDR_ADDR_RAM		0x00010000
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| #define CONFIG_BS_HDR_ADDR_FLASH	0x00800000
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| #define CONFIG_BS_HDR_SIZE		0x00002000
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| #define CONFIG_BS_ADDR_RAM		0x00012000
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| #define CONFIG_BS_ADDR_FLASH		0x00802000
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| #define CONFIG_BS_SIZE			0x00001000
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| 
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| #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
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| #else
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| 
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| /* The bootscript header address is different for B4860 because the NOR
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|  * mapping is different on B4 due to reduced NOR size.
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|  */
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| #if defined(CONFIG_B4860QDS)
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| #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
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| #elif defined(CONFIG_FSL_CORENET)
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| #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
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| #elif defined(CONFIG_BSC9132QDS)
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| #define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
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| #elif defined(CONFIG_C29XPCIE)
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| #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
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| #else
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| #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
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| #endif
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| 
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| #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
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| 
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| #include <config_fsl_chain_trust.h>
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| #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
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| #endif
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