397 lines
11 KiB
C
397 lines
11 KiB
C
/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*
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* SPDX-License-Identifier: Intel
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*/
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#include <common.h>
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#include <asm/arch/mrc.h>
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#include <asm/arch/msg_port.h>
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#include "mrc_util.h"
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#include "hte.h"
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/**
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* Enable HTE to detect all possible errors for the given training parameters
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* (per-bit or full byte lane).
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*/
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static void hte_enable_all_errors(void)
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{
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msg_port_write(HTE, 0x000200a2, 0xffffffff);
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msg_port_write(HTE, 0x000200a3, 0x000000ff);
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msg_port_write(HTE, 0x000200a4, 0x00000000);
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}
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/**
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* Go and read the HTE register in order to find any error
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*
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* @return: The errors detected in the HTE status register
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*/
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static u32 hte_check_errors(void)
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{
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return msg_port_read(HTE, 0x000200a7);
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}
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/**
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* Wait until HTE finishes
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*/
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static void hte_wait_for_complete(void)
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{
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u32 tmp;
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ENTERFN();
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do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0);
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tmp = msg_port_read(HTE, 0x00020011);
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tmp |= (1 << 9);
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tmp &= ~((1 << 12) | (1 << 13));
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msg_port_write(HTE, 0x00020011, tmp);
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LEAVEFN();
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}
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/**
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* Clear registers related with errors in the HTE
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*/
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static void hte_clear_error_regs(void)
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{
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u32 tmp;
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/*
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* Clear all HTE errors and enable error checking
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* for burst and chunk.
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*/
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tmp = msg_port_read(HTE, 0x000200a1);
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tmp |= (1 << 8);
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msg_port_write(HTE, 0x000200a1, tmp);
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}
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/**
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* Execute a basic single-cache-line memory write/read/verify test using simple
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* constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
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*
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* See hte_basic_write_read() which is the external visible wrapper.
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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* @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
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u8 first_run, u8 mode)
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{
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u32 pattern;
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u32 offset;
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if (first_run) {
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msg_port_write(HTE, 0x00020020, 0x01b10021);
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msg_port_write(HTE, 0x00020021, 0x06000000);
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msg_port_write(HTE, 0x00020022, addr >> 6);
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msg_port_write(HTE, 0x00020062, 0x00800015);
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msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
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msg_port_write(HTE, 0x00020064, 0xcccccccc);
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msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
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msg_port_write(HTE, 0x00020061, 0x00030008);
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if (mode == WRITE_TRAIN)
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pattern = 0xc33c0000;
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else /* READ_TRAIN */
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pattern = 0xaa5555aa;
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for (offset = 0x80; offset <= 0x8f; offset++)
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msg_port_write(HTE, offset, pattern);
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}
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msg_port_write(HTE, 0x000200a1, 0xffff1000);
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msg_port_write(HTE, 0x00020011, 0x00011000);
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msg_port_write(HTE, 0x00020011, 0x00011100);
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hte_wait_for_complete();
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/*
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* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
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* any bytelane errors.
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*/
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return (hte_check_errors() >> 8) & 0xff;
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}
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/**
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* Examine a single-cache-line memory with write/read/verify test using multiple
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* data patterns (victim-aggressor algorithm).
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*
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* See hte_write_stress_bit_lanes() which is the external visible wrapper.
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @loop_cnt: number of test iterations
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* @seed_victim: victim data pattern seed
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* @seed_aggressor: aggressor data pattern seed
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* @victim_bit: should be 0 as auto-rotate feature is in use
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
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u8 loop_cnt, u32 seed_victim, u32 seed_aggressor,
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u8 victim_bit, u8 first_run)
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{
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u32 offset;
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u32 tmp;
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if (first_run) {
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msg_port_write(HTE, 0x00020020, 0x00910024);
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msg_port_write(HTE, 0x00020023, 0x00810024);
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msg_port_write(HTE, 0x00020021, 0x06070000);
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msg_port_write(HTE, 0x00020024, 0x06070000);
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msg_port_write(HTE, 0x00020022, addr >> 6);
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msg_port_write(HTE, 0x00020025, addr >> 6);
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msg_port_write(HTE, 0x00020062, 0x0000002a);
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msg_port_write(HTE, 0x00020063, seed_victim);
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msg_port_write(HTE, 0x00020064, seed_aggressor);
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msg_port_write(HTE, 0x00020065, seed_victim);
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/*
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* Write the pattern buffers to select the victim bit
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*
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* Start with bit0
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*/
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for (offset = 0x80; offset <= 0x8f; offset++) {
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if ((offset % 8) == victim_bit)
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msg_port_write(HTE, offset, 0x55555555);
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else
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msg_port_write(HTE, offset, 0xcccccccc);
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}
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msg_port_write(HTE, 0x00020061, 0x00000000);
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msg_port_write(HTE, 0x00020066, 0x03440000);
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msg_port_write(HTE, 0x000200a1, 0xffff1000);
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}
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tmp = 0x10001000 | (loop_cnt << 16);
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msg_port_write(HTE, 0x00020011, tmp);
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msg_port_write(HTE, 0x00020011, tmp | (1 << 8));
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hte_wait_for_complete();
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/*
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* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
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* any bytelane errors.
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*/
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return (hte_check_errors() >> 8) & 0xff;
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}
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/**
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* Use HW HTE engine to initialize or test all memory attached to a given DUNIT.
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* If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to
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* initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5
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* pattern to all memory locations on the RankMask and then read it back.
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* Then it sends an A55AA55A pattern to all memory locations on the RankMask
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* and reads it back.
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*
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* @mrc_params: host structure for all MRC global data
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* @flag: MRC_MEM_INIT or MRC_MEM_TEST
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*
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* @return: errors register showing HTE failures. Also prints out which rank
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* failed the HTE test if failure occurs. For rank detection to work,
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* the address map must be left in its default state. If MRC changes
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* the address map, this function must be modified to change it back
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* to default at the beginning, then restore it at the end.
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*/
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u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
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{
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u32 offset;
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int test_num;
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int i;
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/*
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* Clear out the error registers at the start of each memory
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* init or memory test run.
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*/
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hte_clear_error_regs();
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msg_port_write(HTE, 0x00020062, 0x00000015);
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for (offset = 0x80; offset <= 0x8f; offset++)
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msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5));
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msg_port_write(HTE, 0x00020021, 0x00000000);
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msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
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msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
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msg_port_write(HTE, 0x00020064, 0xcccccccc);
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msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
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msg_port_write(HTE, 0x00020066, 0x03000000);
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switch (flag) {
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case MRC_MEM_INIT:
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/*
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* Only 1 write pass through memory is needed
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* to initialize ECC
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*/
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test_num = 1;
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break;
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case MRC_MEM_TEST:
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/* Write/read then write/read with inverted pattern */
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test_num = 4;
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break;
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default:
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DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
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return 0xffffffff;
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}
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DPF(D_INFO, "hte_mem_init");
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for (i = 0; i < test_num; i++) {
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DPF(D_INFO, ".");
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if (i == 0) {
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msg_port_write(HTE, 0x00020061, 0x00000000);
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msg_port_write(HTE, 0x00020020, 0x00110010);
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} else if (i == 1) {
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msg_port_write(HTE, 0x00020061, 0x00000000);
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msg_port_write(HTE, 0x00020020, 0x00010010);
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} else if (i == 2) {
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msg_port_write(HTE, 0x00020061, 0x00010100);
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msg_port_write(HTE, 0x00020020, 0x00110010);
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} else {
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msg_port_write(HTE, 0x00020061, 0x00010100);
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msg_port_write(HTE, 0x00020020, 0x00010010);
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}
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msg_port_write(HTE, 0x00020011, 0x00111000);
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msg_port_write(HTE, 0x00020011, 0x00111100);
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hte_wait_for_complete();
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/* If this is a READ pass, check for errors at the end */
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if ((i % 2) == 1) {
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/* Return immediately if error */
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if (hte_check_errors())
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break;
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}
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}
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DPF(D_INFO, "done\n");
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return hte_check_errors();
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}
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/**
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* Execute a basic single-cache-line memory write/read/verify test using simple
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* constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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* @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
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u8 first_run, u8 mode)
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{
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u16 errors;
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ENTERFN();
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/* Enable all error reporting in preparation for HTE test */
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hte_enable_all_errors();
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hte_clear_error_regs();
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errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode);
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LEAVEFN();
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return errors;
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}
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/**
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* Examine a single-cache-line memory with write/read/verify test using multiple
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* data patterns (victim-aggressor algorithm).
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*
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* @mrc_params: host structure for all MRC global data
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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*
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* @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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*/
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u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
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u32 addr, u8 first_run)
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{
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u16 errors;
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u8 victim_bit = 0;
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ENTERFN();
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/* Enable all error reporting in preparation for HTE test */
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hte_enable_all_errors();
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hte_clear_error_regs();
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/*
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* Loop through each bit in the bytelane.
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*
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* Each pass creates a victim bit while keeping all other bits the same
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* as aggressors. AVN HTE adds an auto-rotate feature which allows us
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* to program the entire victim/aggressor sequence in 1 step.
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*
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* The victim bit rotates on each pass so no need to have software
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* implement a victim bit loop like on VLV.
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*/
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errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT,
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HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED,
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victim_bit, first_run);
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LEAVEFN();
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return errors;
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}
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/**
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* Execute a basic single-cache-line memory write or read.
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* This is just for receive enable / fine write-levelling purpose.
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*
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* @addr: memory adress being tested (must hit specific channel/rank)
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* @first_run: if set then the HTE registers are configured, otherwise it is
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* assumed configuration is done and we just re-run the test
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* @is_write: when non-zero memory write operation executed, otherwise read
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*/
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void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
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{
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u32 offset;
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u32 tmp;
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hte_enable_all_errors();
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hte_clear_error_regs();
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if (first_run) {
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tmp = is_write ? 0x01110021 : 0x01010021;
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msg_port_write(HTE, 0x00020020, tmp);
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msg_port_write(HTE, 0x00020021, 0x06000000);
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msg_port_write(HTE, 0x00020022, addr >> 6);
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msg_port_write(HTE, 0x00020062, 0x00800015);
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msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
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msg_port_write(HTE, 0x00020064, 0xcccccccc);
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msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
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msg_port_write(HTE, 0x00020061, 0x00030008);
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for (offset = 0x80; offset <= 0x8f; offset++)
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msg_port_write(HTE, offset, 0xc33c0000);
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}
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msg_port_write(HTE, 0x000200a1, 0xffff1000);
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msg_port_write(HTE, 0x00020011, 0x00011000);
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msg_port_write(HTE, 0x00020011, 0x00011100);
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hte_wait_for_complete();
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}
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