137 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
			
		
		
	
	
			137 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
| // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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| /*
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|  * Copyright (C) 2021-2022 Microchip Technology Inc.
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|  * Padmarao Begari <padmarao.begari@microchip.com>
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|  */
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| 
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| /dts-v1/;
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| 
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| #include "microchip-mpfs.dtsi"
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| 
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| /* Clock frequency (in Hz) of the rtcclk */
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| #define RTCCLK_FREQ		1000000
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| 
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| / {
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| 	model = "Microchip PolarFire-SoC Icicle Kit";
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| 	compatible = "microchip,mpfs-icicle-reference-rtlv2210",
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| 		     "microchip,mpfs-icicle-kit", "microchip,mpfs";
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| 
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| 	aliases {
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| 		serial1 = &uart1;
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| 		ethernet0 = &mac1;
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| 		spi0 = &qspi;
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| 	};
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| 
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| 	chosen {
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| 		stdout-path = "serial1";
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| 	};
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| 
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| 	cpus {
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| 		timebase-frequency = <RTCCLK_FREQ>;
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| 	};
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| 
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| 	ddrc_cache_lo: memory@80000000 {
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| 		device_type = "memory";
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| 		reg = <0x0 0x80000000 0x0 0x40000000>;
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| 		status = "okay";
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| 	};
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| 
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| 	ddrc_cache_hi: memory@1040000000 {
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| 		device_type = "memory";
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| 		reg = <0x10 0x40000000 0x0 0x40000000>;
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| 		status = "okay";
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| 	};
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| 
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| 	reserved-memory {
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| 		#address-cells = <2>;
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| 		#size-cells = <2>;
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| 		ranges;
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| 
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| 		hss_payload: region@BFC00000 {
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| 			reg = <0x0 0xBFC00000 0x0 0x400000>;
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| 			no-map;
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| 		};
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| 	};
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| };
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| 
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| &refclk {
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| 	clock-frequency = <125000000>;
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| };
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| 
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| &uart1 {
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| 	status = "okay";
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| };
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| 
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| &mmc {
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| 	status = "okay";
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| 
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| 	bus-width = <4>;
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| 	disable-wp;
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| 	cap-mmc-highspeed;
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| 	cap-sd-highspeed;
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| 	card-detect-delay = <200>;
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| 	mmc-ddr-1_8v;
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| 	mmc-hs200-1_8v;
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| 	sd-uhs-sdr12;
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| 	sd-uhs-sdr25;
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| 	sd-uhs-sdr50;
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| 	sd-uhs-sdr104;
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| };
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| 
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| &i2c1 {
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| 	status = "okay";
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| 	clock-frequency = <100000>;
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| 
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| 	pac193x: pac193x@10 {
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| 		compatible = "microchip,pac1934";
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| 		reg = <0x10>;
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| 		samp-rate = <64>;
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| 		status = "okay";
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| 		ch1: channel0 {
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| 			uohms-shunt-res = <10000>;
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| 			rail-name = "VDDREG";
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| 			channel_enabled;
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| 		};
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| 		ch2: channel1 {
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| 			uohms-shunt-res = <10000>;
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| 			rail-name = "VDDA25";
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| 			channel_enabled;
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| 		};
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| 		ch3: channel2 {
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| 			uohms-shunt-res = <10000>;
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| 			rail-name = "VDD25";
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| 			channel_enabled;
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| 		};
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| 		ch4: channel3 {
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| 			uohms-shunt-res = <10000>;
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| 			rail-name = "VDDA_REG";
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| 			channel_enabled;
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| 		};
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| 	};
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| };
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| 
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| &mac1 {
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| 	status = "okay";
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| 	phy-mode = "sgmii";
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| 	phy-handle = <&phy1>;
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| 	phy1: ethernet-phy@9 {
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| 		reg = <9>;
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| 		ti,fifo-depth = <0x1>;
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| 	};
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| };
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| 
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| &qspi {
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| 	status = "okay";
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| 	num-cs = <1>;
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| 
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| 	flash0: flash@0 {
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| 		compatible = "spi-nand";
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| 		reg = <0x0>;
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| 		spi-tx-bus-width = <4>;
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| 		spi-rx-bus-width = <4>;
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| 		spi-max-frequency = <20000000>;
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| 		spi-cpol;
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| 		spi-cpha;
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| 	};
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| };
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