77 lines
1.4 KiB
C
77 lines
1.4 KiB
C
/*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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u32 get_cpu_rev(void)
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{
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return 0;
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}
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int arch_cpu_init(void)
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{
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configure_clocks();
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/*
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* Configure the memory protection unit (MPU)
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* 0x00000000 - 0xffffffff: Strong-order, Shareable
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* 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable
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*/
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/* Disable MPU */
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writel(0, &V7M_MPU->ctrl);
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writel(
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0x00000000 /* address */
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| 1 << 4 /* VALID */
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| 0 << 0 /* REGION */
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, &V7M_MPU->rbar
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);
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/* Strong-order, Shareable */
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/* TEX=000, S=1, C=0, B=0*/
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writel(
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(V7M_MPU_RASR_XN_ENABLE
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| V7M_MPU_RASR_AP_RW_RW
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| 0x01 << V7M_MPU_RASR_S_SHIFT
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| 0x00 << V7M_MPU_RASR_TEX_SHIFT
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| V7M_MPU_RASR_SIZE_4GB
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| V7M_MPU_RASR_EN)
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, &V7M_MPU->rasr
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);
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writel(
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0xC0000000 /* address */
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| 1 << 4 /* VALID */
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| 1 << 0 /* REGION */
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, &V7M_MPU->rbar
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);
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/* Normal, Outer and inner Non-cacheable */
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/* TEX=001, S=0, C=0, B=0*/
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writel(
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(V7M_MPU_RASR_XN_ENABLE
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| V7M_MPU_RASR_AP_RW_RW
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| 0x01 << V7M_MPU_RASR_TEX_SHIFT
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| V7M_MPU_RASR_SIZE_8MB
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| V7M_MPU_RASR_EN)
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, &V7M_MPU->rasr
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);
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/* Enable MPU */
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writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
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return 0;
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}
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void s_init(void)
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{
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}
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