507 lines
12 KiB
C
507 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Ingenic JZ MMC driver
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*
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* Copyright (c) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#include <errno.h>
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#include <dm/device_compat.h>
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#include <mach/jz4780.h>
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#include <wait_bit.h>
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/* Registers */
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#define MSC_STRPCL 0x000
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#define MSC_STAT 0x004
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#define MSC_CLKRT 0x008
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#define MSC_CMDAT 0x00c
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#define MSC_RESTO 0x010
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#define MSC_RDTO 0x014
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#define MSC_BLKLEN 0x018
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#define MSC_NOB 0x01c
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#define MSC_SNOB 0x020
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#define MSC_IMASK 0x024
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#define MSC_IREG 0x028
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#define MSC_CMD 0x02c
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#define MSC_ARG 0x030
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#define MSC_RES 0x034
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#define MSC_RXFIFO 0x038
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#define MSC_TXFIFO 0x03c
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#define MSC_LPM 0x040
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#define MSC_DMAC 0x044
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#define MSC_DMANDA 0x048
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#define MSC_DMADA 0x04c
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#define MSC_DMALEN 0x050
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#define MSC_DMACMD 0x054
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#define MSC_CTRL2 0x058
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#define MSC_RTCNT 0x05c
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#define MSC_DBG 0x0fc
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/* MSC Clock and Control Register (MSC_STRPCL) */
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#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
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#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
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#define MSC_STRPCL_START_READWAIT BIT(5)
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#define MSC_STRPCL_STOP_READWAIT BIT(4)
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#define MSC_STRPCL_RESET BIT(3)
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#define MSC_STRPCL_START_OP BIT(2)
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#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
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#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
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/* MSC Status Register (MSC_STAT) */
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#define MSC_STAT_AUTO_CMD_DONE BIT(31)
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#define MSC_STAT_IS_RESETTING BIT(15)
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#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
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#define MSC_STAT_PRG_DONE BIT(13)
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#define MSC_STAT_DATA_TRAN_DONE BIT(12)
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#define MSC_STAT_END_CMD_RES BIT(11)
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#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
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#define MSC_STAT_IS_READWAIT BIT(9)
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#define MSC_STAT_CLK_EN BIT(8)
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#define MSC_STAT_DATA_FIFO_FULL BIT(7)
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#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
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#define MSC_STAT_CRC_RES_ERR BIT(5)
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#define MSC_STAT_CRC_READ_ERROR BIT(4)
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#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
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#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
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#define MSC_STAT_TIME_OUT_RES BIT(1)
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#define MSC_STAT_TIME_OUT_READ BIT(0)
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/* MSC Bus Clock Control Register (MSC_CLKRT) */
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#define MSC_CLKRT_CLK_RATE_MASK 0x7
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/* MSC Command Sequence Control Register (MSC_CMDAT) */
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#define MSC_CMDAT_IO_ABORT BIT(11)
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#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
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#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
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#define MSC_CMDAT_DMA_EN BIT(8)
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#define MSC_CMDAT_INIT BIT(7)
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#define MSC_CMDAT_BUSY BIT(6)
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#define MSC_CMDAT_STREAM_BLOCK BIT(5)
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#define MSC_CMDAT_WRITE BIT(4)
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#define MSC_CMDAT_DATA_EN BIT(3)
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#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
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#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
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#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
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#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
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#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
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#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
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#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
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#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
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/* MSC Interrupts Mask Register (MSC_IMASK) */
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#define MSC_IMASK_TIME_OUT_RES BIT(9)
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#define MSC_IMASK_TIME_OUT_READ BIT(8)
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#define MSC_IMASK_SDIO BIT(7)
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#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
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#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
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#define MSC_IMASK_END_CMD_RES BIT(2)
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#define MSC_IMASK_PRG_DONE BIT(1)
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#define MSC_IMASK_DATA_TRAN_DONE BIT(0)
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/* MSC Interrupts Status Register (MSC_IREG) */
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#define MSC_IREG_TIME_OUT_RES BIT(9)
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#define MSC_IREG_TIME_OUT_READ BIT(8)
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#define MSC_IREG_SDIO BIT(7)
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#define MSC_IREG_TXFIFO_WR_REQ BIT(6)
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#define MSC_IREG_RXFIFO_RD_REQ BIT(5)
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#define MSC_IREG_END_CMD_RES BIT(2)
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#define MSC_IREG_PRG_DONE BIT(1)
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#define MSC_IREG_DATA_TRAN_DONE BIT(0)
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struct jz_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct jz_mmc_priv {
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void __iomem *regs;
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u32 flags;
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/* priv flags */
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#define JZ_MMC_BUS_WIDTH_MASK 0x3
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#define JZ_MMC_BUS_WIDTH_1 0x0
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#define JZ_MMC_BUS_WIDTH_4 0x2
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#define JZ_MMC_BUS_WIDTH_8 0x3
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#define JZ_MMC_SENT_INIT BIT(2)
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};
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static int jz_mmc_clock_rate(void)
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{
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return 24000000;
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}
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#if CONFIG_IS_ENABLED(MMC_WRITE)
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static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
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{
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int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
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const void *buf = data->src;
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while (sz--) {
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u32 val = get_unaligned_le32(buf);
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wait_for_bit_le32(priv->regs + MSC_IREG,
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MSC_IREG_TXFIFO_WR_REQ,
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true, 10000, false);
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writel(val, priv->regs + MSC_TXFIFO);
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buf += 4;
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}
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}
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#else
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static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
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{}
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#endif
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static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
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{
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int sz = data->blocks * data->blocksize;
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void *buf = data->dest;
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u32 stat, val;
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do {
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stat = readl(priv->regs + MSC_STAT);
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if (stat & MSC_STAT_TIME_OUT_READ)
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return -ETIMEDOUT;
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if (stat & MSC_STAT_CRC_READ_ERROR)
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return -EINVAL;
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if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
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udelay(10);
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continue;
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}
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do {
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val = readl(priv->regs + MSC_RXFIFO);
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if (sz == 1)
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*(u8 *)buf = (u8)val;
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else if (sz == 2)
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put_unaligned_le16(val, buf);
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else if (sz >= 4)
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put_unaligned_le32(val, buf);
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buf += 4;
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sz -= 4;
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stat = readl(priv->regs + MSC_STAT);
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} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
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} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
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return 0;
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}
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static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
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struct mmc_cmd *cmd, struct mmc_data *data)
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{
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u32 stat, mask, cmdat = 0;
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int i, ret;
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/* stop the clock */
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writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
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ret = wait_for_bit_le32(priv->regs + MSC_STAT,
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MSC_STAT_CLK_EN, false, 10000, false);
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if (ret)
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return ret;
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writel(0, priv->regs + MSC_DMAC);
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/* setup command */
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writel(cmd->cmdidx, priv->regs + MSC_CMD);
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writel(cmd->cmdarg, priv->regs + MSC_ARG);
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if (data) {
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/* setup data */
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cmdat |= MSC_CMDAT_DATA_EN;
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if (data->flags & MMC_DATA_WRITE)
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cmdat |= MSC_CMDAT_WRITE;
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writel(data->blocks, priv->regs + MSC_NOB);
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writel(data->blocksize, priv->regs + MSC_BLKLEN);
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} else {
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writel(0, priv->regs + MSC_NOB);
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writel(0, priv->regs + MSC_BLKLEN);
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}
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/* setup response */
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switch (cmd->resp_type) {
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case MMC_RSP_NONE:
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break;
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case MMC_RSP_R1:
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case MMC_RSP_R1b:
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cmdat |= MSC_CMDAT_RESPONSE_R1;
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break;
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case MMC_RSP_R2:
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cmdat |= MSC_CMDAT_RESPONSE_R2;
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break;
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case MMC_RSP_R3:
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cmdat |= MSC_CMDAT_RESPONSE_R3;
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break;
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default:
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break;
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}
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if (cmd->resp_type & MMC_RSP_BUSY)
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cmdat |= MSC_CMDAT_BUSY;
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/* set init for the first command only */
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if (!(priv->flags & JZ_MMC_SENT_INIT)) {
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cmdat |= MSC_CMDAT_INIT;
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priv->flags |= JZ_MMC_SENT_INIT;
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}
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cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
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/* write the data setup */
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writel(cmdat, priv->regs + MSC_CMDAT);
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/* unmask interrupts */
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mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
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if (data) {
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mask &= ~MSC_IMASK_DATA_TRAN_DONE;
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if (data->flags & MMC_DATA_WRITE) {
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mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
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} else {
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mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
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MSC_IMASK_TIME_OUT_READ);
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}
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}
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writel(mask, priv->regs + MSC_IMASK);
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/* clear interrupts */
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writel(0xffffffff, priv->regs + MSC_IREG);
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/* start the command (& the clock) */
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writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
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priv->regs + MSC_STRPCL);
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/* wait for completion */
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for (i = 0; i < 100; i++) {
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stat = readl(priv->regs + MSC_IREG);
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stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
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if (stat)
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break;
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mdelay(1);
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}
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writel(stat, priv->regs + MSC_IREG);
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if (stat & MSC_IREG_TIME_OUT_RES)
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return -ETIMEDOUT;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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/* read the response */
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if (cmd->resp_type & MMC_RSP_136) {
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u16 a, b, c, i;
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a = readw(priv->regs + MSC_RES);
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for (i = 0; i < 4; i++) {
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b = readw(priv->regs + MSC_RES);
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c = readw(priv->regs + MSC_RES);
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cmd->response[i] =
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(a << 24) | (b << 8) | (c >> 8);
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a = c;
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}
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} else {
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cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
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cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
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cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
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}
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}
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if (data) {
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if (data->flags & MMC_DATA_WRITE)
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jz_mmc_write_data(priv, data);
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else if (data->flags & MMC_DATA_READ) {
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ret = jz_mmc_read_data(priv, data);
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
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{
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u32 real_rate = jz_mmc_clock_rate();
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u8 clk_div = 0;
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/* calculate clock divide */
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while ((real_rate > mmc->clock) && (clk_div < 7)) {
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real_rate >>= 1;
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clk_div++;
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}
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writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
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/* set the bus width for the next command */
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priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
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if (mmc->bus_width == 8)
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priv->flags |= JZ_MMC_BUS_WIDTH_8;
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else if (mmc->bus_width == 4)
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priv->flags |= JZ_MMC_BUS_WIDTH_4;
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else
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priv->flags |= JZ_MMC_BUS_WIDTH_1;
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return 0;
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}
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static int jz_mmc_core_init(struct mmc *mmc)
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{
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struct jz_mmc_priv *priv = mmc->priv;
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int ret;
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/* Reset */
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writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
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ret = wait_for_bit_le32(priv->regs + MSC_STAT,
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MSC_STAT_IS_RESETTING, false, 10000, false);
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if (ret)
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return ret;
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/* Maximum timeouts */
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writel(0xffff, priv->regs + MSC_RESTO);
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writel(0xffffffff, priv->regs + MSC_RDTO);
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/* Enable low power mode */
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writel(0x1, priv->regs + MSC_LPM);
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct jz_mmc_priv *priv = mmc->priv;
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return jz_mmc_send_cmd(mmc, priv, cmd, data);
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}
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static int jz_mmc_legacy_set_ios(struct mmc *mmc)
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{
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struct jz_mmc_priv *priv = mmc->priv;
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return jz_mmc_set_ios(mmc, priv);
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};
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static const struct mmc_ops jz_msc_ops = {
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.send_cmd = jz_mmc_legacy_send_cmd,
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.set_ios = jz_mmc_legacy_set_ios,
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.init = jz_mmc_core_init,
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};
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static struct jz_mmc_priv jz_mmc_priv_static;
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static struct jz_mmc_plat jz_mmc_plat_static = {
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.cfg = {
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.name = "MSC",
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.ops = &jz_msc_ops,
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.voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
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MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
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MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
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.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
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.f_min = 375000,
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.f_max = 48000000,
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.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
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},
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};
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int jz_mmc_init(void __iomem *base)
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{
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struct mmc *mmc;
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jz_mmc_priv_static.regs = base;
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mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
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return mmc ? 0 : -ENODEV;
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}
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#else /* CONFIG_DM_MMC */
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct jz_mmc_priv *priv = dev_get_priv(dev);
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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return jz_mmc_send_cmd(mmc, priv, cmd, data);
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}
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static int jz_mmc_dm_set_ios(struct udevice *dev)
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{
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struct jz_mmc_priv *priv = dev_get_priv(dev);
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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return jz_mmc_set_ios(mmc, priv);
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};
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static const struct dm_mmc_ops jz_msc_ops = {
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.send_cmd = jz_mmc_dm_send_cmd,
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.set_ios = jz_mmc_dm_set_ios,
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};
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static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
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{
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struct jz_mmc_priv *priv = dev_get_priv(dev);
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struct jz_mmc_plat *plat = dev_get_platdata(dev);
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struct mmc_config *cfg;
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int ret;
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priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
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cfg = &plat->cfg;
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cfg->name = "MSC";
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cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
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ret = mmc_of_parse(dev, cfg);
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if (ret < 0) {
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dev_err(dev, "failed to parse host caps\n");
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return ret;
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}
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cfg->f_min = 400000;
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cfg->f_max = 52000000;
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
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return 0;
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}
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static int jz_mmc_bind(struct udevice *dev)
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{
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struct jz_mmc_plat *plat = dev_get_platdata(dev);
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|
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return mmc_bind(dev, &plat->mmc, &plat->cfg);
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|
}
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|
|
|
static int jz_mmc_probe(struct udevice *dev)
|
|
{
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct jz_mmc_priv *priv = dev_get_priv(dev);
|
|
struct jz_mmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
plat->mmc.priv = priv;
|
|
upriv->mmc = &plat->mmc;
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|
return jz_mmc_core_init(&plat->mmc);
|
|
}
|
|
|
|
static const struct udevice_id jz_mmc_ids[] = {
|
|
{ .compatible = "ingenic,jz4780-mmc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(jz_mmc_drv) = {
|
|
.name = "jz_mmc",
|
|
.id = UCLASS_MMC,
|
|
.of_match = jz_mmc_ids,
|
|
.ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
|
|
.bind = jz_mmc_bind,
|
|
.probe = jz_mmc_probe,
|
|
.priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
|
|
.ops = &jz_msc_ops,
|
|
};
|
|
#endif /* CONFIG_DM_MMC */
|