297 lines
7.1 KiB
C
297 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <misc.h>
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#include <net.h>
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#include <pci_ids.h>
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#include <linux/list.h>
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#include <asm/arch/board.h>
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#include <asm/arch/csrs/csrs-cgx.h>
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#include <asm/io.h>
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#include "cgx.h"
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char lmac_type_to_str[][8] = {
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"SGMII",
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"XAUI",
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"RXAUI",
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"10G_R",
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"40G_R",
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"RGMII",
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"QSGMII",
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"25G_R",
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"50G_R",
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"100G_R",
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"USXGMII",
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};
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char lmac_speed_to_str[][8] = {
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"0",
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"10M",
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"100M",
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"1G",
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"2.5G",
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"5G",
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"10G",
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"20G",
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"25G",
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"40G",
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"50G",
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"80G",
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"100G",
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};
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/**
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* Given an LMAC/PF instance number, return the lmac
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* Per design, each PF has only one LMAC mapped.
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*
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* @param instance instance to find
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*
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* Return: pointer to lmac data structure or NULL if not found
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*/
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struct lmac *nix_get_cgx_lmac(int lmac_instance)
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{
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struct cgx *cgx;
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struct udevice *dev;
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int i, idx, err;
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for (i = 0; i < CGX_PER_NODE; i++) {
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err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVICE_ID_OCTEONTX2_CGX, i,
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&dev);
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if (err)
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continue;
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cgx = dev_get_priv(dev);
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debug("%s udev %p cgx %p instance %d\n", __func__, dev, cgx,
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lmac_instance);
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for (idx = 0; idx < cgx->lmac_count; idx++) {
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if (cgx->lmac[idx]->instance == lmac_instance)
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return cgx->lmac[idx];
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}
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}
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return NULL;
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}
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void cgx_lmac_mac_filter_clear(struct lmac *lmac)
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{
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union cgxx_cmrx_rx_dmac_ctl0 dmac_ctl0;
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union cgxx_cmr_rx_dmacx_cam0 dmac_cam0;
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void *reg_addr;
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dmac_cam0.u = 0x0;
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reg_addr = lmac->cgx->reg_base +
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CGXX_CMR_RX_DMACX_CAM0(lmac->lmac_id * 8);
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writeq(dmac_cam0.u, reg_addr);
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debug("%s: reg %p dmac_cam0 %llx\n", __func__, reg_addr, dmac_cam0.u);
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dmac_ctl0.u = 0x0;
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dmac_ctl0.s.bcst_accept = 1;
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dmac_ctl0.s.mcst_mode = 1;
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dmac_ctl0.s.cam_accept = 0;
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reg_addr = lmac->cgx->reg_base +
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CGXX_CMRX_RX_DMAC_CTL0(lmac->lmac_id);
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writeq(dmac_ctl0.u, reg_addr);
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debug("%s: reg %p dmac_ctl0 %llx\n", __func__, reg_addr, dmac_ctl0.u);
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}
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void cgx_lmac_mac_filter_setup(struct lmac *lmac)
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{
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union cgxx_cmrx_rx_dmac_ctl0 dmac_ctl0;
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union cgxx_cmr_rx_dmacx_cam0 dmac_cam0;
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u64 mac, tmp;
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void *reg_addr;
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memcpy((void *)&tmp, lmac->mac_addr, 6);
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debug("%s: tmp %llx\n", __func__, tmp);
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debug("%s: swab tmp %llx\n", __func__, swab64(tmp));
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mac = swab64(tmp) >> 16;
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debug("%s: mac %llx\n", __func__, mac);
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dmac_cam0.u = 0x0;
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dmac_cam0.s.id = lmac->lmac_id;
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dmac_cam0.s.adr = mac;
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dmac_cam0.s.en = 1;
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reg_addr = lmac->cgx->reg_base +
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CGXX_CMR_RX_DMACX_CAM0(lmac->lmac_id * 8);
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writeq(dmac_cam0.u, reg_addr);
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debug("%s: reg %p dmac_cam0 %llx\n", __func__, reg_addr, dmac_cam0.u);
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dmac_ctl0.u = 0x0;
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dmac_ctl0.s.bcst_accept = 1;
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dmac_ctl0.s.mcst_mode = 0;
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dmac_ctl0.s.cam_accept = 1;
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reg_addr = lmac->cgx->reg_base +
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CGXX_CMRX_RX_DMAC_CTL0(lmac->lmac_id);
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writeq(dmac_ctl0.u, reg_addr);
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debug("%s: reg %p dmac_ctl0 %llx\n", __func__, reg_addr, dmac_ctl0.u);
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}
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int cgx_lmac_set_pkind(struct lmac *lmac, u8 lmac_id, int pkind)
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{
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cgx_write(lmac->cgx, lmac_id, CGXX_CMRX_RX_ID_MAP(0),
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(pkind & 0x3f));
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return 0;
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}
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int cgx_lmac_link_status(struct lmac *lmac, int lmac_id, u64 *status)
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{
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int ret = 0;
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ret = cgx_intf_get_link_sts(lmac->cgx->cgx_id, lmac_id, status);
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if (ret) {
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debug("%s request failed for cgx%d lmac%d\n",
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__func__, lmac->cgx->cgx_id, lmac->lmac_id);
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ret = -1;
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}
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return ret;
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}
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int cgx_lmac_rx_tx_enable(struct lmac *lmac, int lmac_id, bool enable)
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{
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struct cgx *cgx = lmac->cgx;
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union cgxx_cmrx_config cmrx_config;
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if (!cgx || lmac_id >= cgx->lmac_count)
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return -ENODEV;
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cmrx_config.u = cgx_read(cgx, lmac_id, CGXX_CMRX_CONFIG(0));
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cmrx_config.s.data_pkt_rx_en =
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cmrx_config.s.data_pkt_tx_en = enable ? 1 : 0;
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cgx_write(cgx, lmac_id, CGXX_CMRX_CONFIG(0), cmrx_config.u);
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return 0;
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}
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int cgx_lmac_link_enable(struct lmac *lmac, int lmac_id, bool enable,
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u64 *status)
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{
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int ret = 0;
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ret = cgx_intf_link_up_dwn(lmac->cgx->cgx_id, lmac_id, enable,
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status);
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if (ret) {
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debug("%s request failed for cgx%d lmac%d\n",
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__func__, lmac->cgx->cgx_id, lmac->lmac_id);
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ret = -1;
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}
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return ret;
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}
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int cgx_lmac_internal_loopback(struct lmac *lmac, int lmac_id, bool enable)
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{
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struct cgx *cgx = lmac->cgx;
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union cgxx_cmrx_config cmrx_cfg;
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union cgxx_gmp_pcs_mrx_control mrx_control;
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union cgxx_spux_control1 spux_control1;
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enum lmac_type lmac_type;
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if (!cgx || lmac_id >= cgx->lmac_count)
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return -ENODEV;
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cmrx_cfg.u = cgx_read(cgx, lmac_id, CGXX_CMRX_CONFIG(0));
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lmac_type = cmrx_cfg.s.lmac_type;
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if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) {
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mrx_control.u = cgx_read(cgx, lmac_id,
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CGXX_GMP_PCS_MRX_CONTROL(0));
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mrx_control.s.loopbck1 = enable ? 1 : 0;
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cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CONTROL(0),
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mrx_control.u);
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} else {
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spux_control1.u = cgx_read(cgx, lmac_id,
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CGXX_SPUX_CONTROL1(0));
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spux_control1.s.loopbck = enable ? 1 : 0;
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cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1(0),
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spux_control1.u);
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}
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return 0;
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}
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static int cgx_lmac_init(struct cgx *cgx)
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{
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struct lmac *lmac;
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union cgxx_cmrx_config cmrx_cfg;
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static int instance = 1;
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int i;
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cgx->lmac_count = cgx_read(cgx, 0, CGXX_CMR_RX_LMACS());
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debug("%s: Found %d lmacs for cgx %d@%p\n", __func__, cgx->lmac_count,
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cgx->cgx_id, cgx->reg_base);
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for (i = 0; i < cgx->lmac_count; i++) {
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lmac = calloc(1, sizeof(*lmac));
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if (!lmac)
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return -ENOMEM;
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lmac->instance = instance++;
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snprintf(lmac->name, sizeof(lmac->name), "cgx_fwi_%d_%d",
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cgx->cgx_id, i);
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/* Get LMAC type */
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cmrx_cfg.u = cgx_read(cgx, i, CGXX_CMRX_CONFIG(0));
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lmac->lmac_type = cmrx_cfg.s.lmac_type;
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lmac->lmac_id = i;
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lmac->cgx = cgx;
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cgx->lmac[i] = lmac;
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debug("%s: map id %d to lmac %p (%s), type:%d instance %d\n",
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__func__, i, lmac, lmac->name, lmac->lmac_type,
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lmac->instance);
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lmac->init_pend = 1;
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printf("CGX%d LMAC%d [%s]\n", lmac->cgx->cgx_id,
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lmac->lmac_id, lmac_type_to_str[lmac->lmac_type]);
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octeontx2_board_get_mac_addr((lmac->instance - 1),
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lmac->mac_addr);
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debug("%s: MAC %pM\n", __func__, lmac->mac_addr);
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cgx_lmac_mac_filter_setup(lmac);
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}
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return 0;
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}
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int cgx_probe(struct udevice *dev)
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{
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struct cgx *cgx = dev_get_priv(dev);
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int err;
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cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
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PCI_REGION_MEM);
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cgx->dev = dev;
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cgx->cgx_id = ((u64)(cgx->reg_base) >> 24) & 0x7;
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debug("%s CGX BAR %p, id: %d\n", __func__, cgx->reg_base,
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cgx->cgx_id);
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debug("%s CGX %p, udev: %p\n", __func__, cgx, dev);
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err = cgx_lmac_init(cgx);
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return err;
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}
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int cgx_remove(struct udevice *dev)
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{
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struct cgx *cgx = dev_get_priv(dev);
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int i;
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debug("%s: cgx remove reg_base %p cgx_id %d",
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__func__, cgx->reg_base, cgx->cgx_id);
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for (i = 0; i < cgx->lmac_count; i++)
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cgx_lmac_mac_filter_clear(cgx->lmac[i]);
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return 0;
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}
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U_BOOT_DRIVER(cgx) = {
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.name = "cgx",
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.id = UCLASS_MISC,
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.probe = cgx_probe,
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.remove = cgx_remove,
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.priv_auto = sizeof(struct cgx),
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};
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static struct pci_device_id cgx_supported[] = {
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{PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_CGX) },
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{}
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};
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U_BOOT_PCI_DEVICE(cgx, cgx_supported);
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