442 lines
12 KiB
C
442 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TI PHY drivers
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*
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*/
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#include <common.h>
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#include <log.h>
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#include <phy.h>
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#include <dm/devres.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <malloc.h>
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#include <dm.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include "ti_phy_init.h"
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/* TI DP83867 */
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#define DP83867_DEVADDR 0x1f
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#define MII_DP83867_PHYCTRL 0x10
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#define MII_DP83867_MICR 0x12
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#define MII_DP83867_CFG2 0x14
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#define MII_DP83867_BISCR 0x16
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#define DP83867_CTRL 0x1f
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/* Extended Registers */
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#define DP83867_CFG4 0x0031
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#define DP83867_RGMIICTL 0x0032
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#define DP83867_STRAP_STS1 0x006E
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#define DP83867_STRAP_STS2 0x006f
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#define DP83867_RGMIIDCTL 0x0086
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#define DP83867_IO_MUX_CFG 0x0170
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#define DP83867_SGMIICTL 0x00D3
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#define DP83867_SW_RESET BIT(15)
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#define DP83867_SW_RESTART BIT(14)
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/* MICR Interrupt bits */
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#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
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#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
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#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
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#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
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#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
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#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
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#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
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#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
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#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
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#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
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#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
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#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
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/* RGMIICTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
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#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
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/* STRAP_STS1 bits */
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#define DP83867_STRAP_STS1_RESERVED BIT(11)
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/* STRAP_STS2 bits */
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#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
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#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
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#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
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#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
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#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
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#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
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#define DP83867_PHYCR_RESERVED_MASK BIT(11)
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#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
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#define DP83867_MDI_CROSSOVER 5
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#define DP83867_MDI_CROSSOVER_MDIX 2
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#define DP83867_PHYCTRL_SGMIIEN 0x0800
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#define DP83867_PHYCTRL_RXFIFO_SHIFT 12
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#define DP83867_PHYCTRL_TXFIFO_SHIFT 14
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/* RGMIIDCTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
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#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
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#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
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/* CFG2 bits */
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#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
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#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
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#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
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#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
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#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
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#define MII_DP83867_CFG2_MASK 0x003F
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/* User setting - can be taken from DTS */
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#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
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/* IO_MUX_CFG bits */
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
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#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
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#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
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GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
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/* CFG4 bits */
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#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
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/* SGMIICTL bits */
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#define DP83867_SGMII_TYPE BIT(14)
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enum {
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DP83867_PORT_MIRRORING_KEEP,
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DP83867_PORT_MIRRORING_EN,
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DP83867_PORT_MIRRORING_DIS,
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};
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struct dp83867_private {
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u32 rx_id_delay;
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u32 tx_id_delay;
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int fifo_depth;
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int io_impedance;
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bool rxctrl_strap_quirk;
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int port_mirroring;
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bool set_clk_output;
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unsigned int clk_output_sel;
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bool sgmii_ref_clk_en;
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};
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static int dp83867_config_port_mirroring(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 =
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(struct dp83867_private *)phydev->priv;
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u16 val;
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val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
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if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
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val |= DP83867_CFG4_PORT_MIRROR_EN;
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else
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val &= ~DP83867_CFG4_PORT_MIRROR_EN;
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
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return 0;
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}
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#if defined(CONFIG_DM_ETH)
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/**
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* dp83867_data_init - Convenience function for setting PHY specific data
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*
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* @phydev: the phy_device struct
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*/
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static int dp83867_of_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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ofnode node;
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int ret;
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node = phy_get_ofnode(phydev);
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if (!ofnode_valid(node))
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return 0;
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/* Optional configuration */
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ret = ofnode_read_u32(node, "ti,clk-output-sel",
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&dp83867->clk_output_sel);
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/* If not set, keep default */
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if (!ret) {
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dp83867->set_clk_output = true;
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/* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
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* DP83867_CLK_O_SEL_OFF.
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*/
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if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
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dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
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pr_debug("ti,clk-output-sel value %u out of range\n",
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dp83867->clk_output_sel);
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return -EINVAL;
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}
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}
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if (ofnode_read_bool(node, "ti,max-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
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else if (ofnode_read_bool(node, "ti,min-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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else
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dp83867->io_impedance = -EINVAL;
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if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
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dp83867->rxctrl_strap_quirk = true;
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/* Existing behavior was to use default pin strapping delay in rgmii
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* mode, but rgmii should have meant no delay. Warn existing users.
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*/
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
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u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_STRAP_STS2);
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u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
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DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
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u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
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DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
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if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
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rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
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pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
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"Should be 'rgmii-id' to use internal delays\n");
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}
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/* RX delay *must* be specified if internal delay of RX is used. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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ret = ofnode_read_u32(node, "ti,rx-internal-delay",
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&dp83867->rx_id_delay);
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if (ret) {
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pr_debug("ti,rx-internal-delay must be specified\n");
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return ret;
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}
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if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
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pr_debug("ti,rx-internal-delay value of %u out of range\n",
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dp83867->rx_id_delay);
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return -EINVAL;
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}
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}
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/* TX delay *must* be specified if internal delay of RX is used. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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ret = ofnode_read_u32(node, "ti,tx-internal-delay",
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&dp83867->tx_id_delay);
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if (ret) {
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debug("ti,tx-internal-delay must be specified\n");
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return ret;
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}
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if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
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pr_debug("ti,tx-internal-delay value of %u out of range\n",
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dp83867->tx_id_delay);
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return -EINVAL;
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}
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}
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dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
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DEFAULT_FIFO_DEPTH);
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if (ofnode_read_bool(node, "enet-phy-lane-swap"))
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dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
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if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
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dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
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if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
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dp83867->sgmii_ref_clk_en = true;
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return 0;
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}
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#else
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static int dp83867_of_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
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dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
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dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
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dp83867->io_impedance = -EINVAL;
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return 0;
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}
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#endif
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static int dp83867_config(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867;
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int val, delay, cfg2;
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int ret, bs;
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dp83867 = (struct dp83867_private *)phydev->priv;
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ret = dp83867_of_init(phydev);
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if (ret)
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return ret;
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/* Restart the PHY. */
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val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
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phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
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val | DP83867_SW_RESTART);
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/* Mode 1 or 2 workaround */
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if (dp83867->rxctrl_strap_quirk) {
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val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_CFG4);
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val &= ~BIT(7);
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phy_write_mmd(phydev, DP83867_DEVADDR,
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DP83867_CFG4, val);
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}
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if (phy_interface_is_rgmii(phydev)) {
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val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
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if (val < 0) {
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ret = val;
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goto err_out;
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}
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val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
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val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
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/* Do not force link good */
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val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
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/* The code below checks if "port mirroring" N/A MODE4 has been
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* enabled during power on bootstrap.
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*
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* Such N/A mode enabled by mistake can put PHY IC in some
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* internal testing mode and disable RGMII transmission.
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*
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* In this particular case one needs to check STRAP_STS1
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* register's bit 11 (marked as RESERVED).
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*/
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bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
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if (bs & DP83867_STRAP_STS1_RESERVED)
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val &= ~DP83867_PHYCR_RESERVED_MASK;
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ret = phy_write(phydev, MDIO_DEVAD_NONE,
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MII_DP83867_PHYCTRL, val);
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val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_RGMIICTL);
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val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
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DP83867_RGMII_RX_CLK_DELAY_EN);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
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DP83867_RGMII_RX_CLK_DELAY_EN);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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val |= DP83867_RGMII_TX_CLK_DELAY_EN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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val |= DP83867_RGMII_RX_CLK_DELAY_EN;
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
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delay = (dp83867->rx_id_delay |
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(dp83867->tx_id_delay <<
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DP83867_RGMII_TX_CLK_DELAY_SHIFT));
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phy_write_mmd(phydev, DP83867_DEVADDR,
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DP83867_RGMIIDCTL, delay);
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}
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if (phy_interface_is_sgmii(phydev)) {
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if (dp83867->sgmii_ref_clk_en)
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
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DP83867_SGMII_TYPE);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
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(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
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cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
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cfg2 &= MII_DP83867_CFG2_MASK;
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cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
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MII_DP83867_CFG2_SGMII_AUTONEGEN |
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MII_DP83867_CFG2_SPEEDOPT_ENH |
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MII_DP83867_CFG2_SPEEDOPT_CNT |
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MII_DP83867_CFG2_SPEEDOPT_INTLOW);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
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phy_write_mmd(phydev, DP83867_DEVADDR,
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DP83867_RGMIICTL, 0x0);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
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DP83867_PHYCTRL_SGMIIEN |
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(DP83867_MDI_CROSSOVER_MDIX <<
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DP83867_MDI_CROSSOVER) |
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(dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
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(dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
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phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
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}
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if (dp83867->io_impedance >= 0) {
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val = phy_read_mmd(phydev,
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DP83867_DEVADDR,
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DP83867_IO_MUX_CFG);
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val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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val |= dp83867->io_impedance &
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DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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phy_write_mmd(phydev, DP83867_DEVADDR,
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DP83867_IO_MUX_CFG, val);
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}
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if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
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dp83867_config_port_mirroring(phydev);
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/* Clock output selection if muxing property is set */
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if (dp83867->set_clk_output) {
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val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_IO_MUX_CFG);
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if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
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val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
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} else {
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val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
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DP83867_IO_MUX_CFG_CLK_O_DISABLE);
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val |= dp83867->clk_output_sel <<
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DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
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}
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phy_write_mmd(phydev, DP83867_DEVADDR,
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DP83867_IO_MUX_CFG, val);
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}
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genphy_config_aneg(phydev);
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return 0;
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err_out:
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return ret;
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}
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static int dp83867_probe(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867;
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dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
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if (!dp83867)
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return -ENOMEM;
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phydev->priv = dp83867;
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return 0;
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}
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static struct phy_driver DP83867_driver = {
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.name = "TI DP83867",
|
|
.uid = 0x2000a231,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.probe = dp83867_probe,
|
|
.config = &dp83867_config,
|
|
.startup = &genphy_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
int phy_dp83867_init(void)
|
|
{
|
|
phy_register(&DP83867_driver);
|
|
return 0;
|
|
}
|