594 lines
18 KiB
C
594 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI autoconfiguration library
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000 MontaVista Software Inc.
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* Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <pci.h>
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#include <time.h>
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#include "pci_internal.h"
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/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
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#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
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#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
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#endif
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static void dm_pciauto_setup_device(struct udevice *dev,
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struct pci_region *mem,
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struct pci_region *prefetch,
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struct pci_region *io)
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{
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u32 bar_response;
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pci_size_t bar_size;
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u16 cmdstat = 0;
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int bar, bar_nr = 0;
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int bars_num;
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u8 header_type;
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int rom_addr;
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pci_addr_t bar_value;
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struct pci_region *bar_res = NULL;
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int found_mem64 = 0;
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u16 class;
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dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
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cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
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PCI_COMMAND_MASTER;
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dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
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header_type &= 0x7f;
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switch (header_type) {
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case PCI_HEADER_TYPE_NORMAL:
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bars_num = 6;
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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bars_num = 2;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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/* CardBus header does not have any BAR */
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bars_num = 0;
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break;
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default:
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/* Skip configuring BARs for unknown header types */
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bars_num = 0;
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break;
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}
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for (bar = PCI_BASE_ADDRESS_0;
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bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
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int ret = 0;
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/* Tickle the BAR and get the response */
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dm_pci_write_config32(dev, bar, 0xffffffff);
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dm_pci_read_config32(dev, bar, &bar_response);
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/* If BAR is not implemented (or invalid) go to the next BAR */
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if (!bar_response || bar_response == 0xffffffff)
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continue;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
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bar_size &= ~(bar_size - 1);
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bar_res = io;
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debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
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bar_nr, (unsigned long long)bar_size);
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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u32 bar_response_upper;
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u64 bar64;
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dm_pci_write_config32(dev, bar + 4, 0xffffffff);
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dm_pci_read_config32(dev, bar + 4,
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&bar_response_upper);
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bar64 = ((u64)bar_response_upper << 32) |
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bar_response;
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bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
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+ 1;
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found_mem64 = 1;
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} else {
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bar_size = (u32)(~(bar_response &
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PCI_BASE_ADDRESS_MEM_MASK) + 1);
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}
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if (prefetch &&
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(bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
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bar_res = prefetch;
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else
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bar_res = mem;
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debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
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bar_nr, bar_res == prefetch ? "Prf" : "Mem",
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found_mem64 ? "64" : "",
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(unsigned long long)bar_size);
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}
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ret = pciauto_region_allocate(bar_res, bar_size,
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&bar_value, found_mem64);
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if (ret)
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printf("PCI: Failed autoconfig bar %x\n", bar);
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if (!ret) {
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/* Write it out and update our limit */
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dm_pci_write_config32(dev, bar, (u32)bar_value);
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if (found_mem64) {
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bar += 4;
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#ifdef CONFIG_SYS_PCI_64BIT
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dm_pci_write_config32(dev, bar,
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(u32)(bar_value >> 32));
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#else
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/*
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* If we are a 64-bit decoder then increment to
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* the upper 32 bits of the bar and force it to
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* locate in the lower 4GB of memory.
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*/
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dm_pci_write_config32(dev, bar, 0x00000000);
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#endif
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}
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}
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cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
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PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
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debug("\n");
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bar_nr++;
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}
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/* Configure the expansion ROM address */
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if (header_type == PCI_HEADER_TYPE_NORMAL ||
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header_type == PCI_HEADER_TYPE_BRIDGE) {
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rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
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PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
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dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
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dm_pci_read_config32(dev, rom_addr, &bar_response);
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if (bar_response) {
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bar_size = -(bar_response & ~1);
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debug("PCI Autoconfig: ROM, size=%#x, ",
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(unsigned int)bar_size);
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if (pciauto_region_allocate(mem, bar_size, &bar_value,
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false) == 0) {
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dm_pci_write_config32(dev, rom_addr, bar_value);
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}
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cmdstat |= PCI_COMMAND_MEMORY;
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debug("\n");
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}
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}
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/* PCI_COMMAND_IO must be set for VGA device */
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dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
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if (class == PCI_CLASS_DISPLAY_VGA)
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cmdstat |= PCI_COMMAND_IO;
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dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
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dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
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CONFIG_SYS_PCI_CACHE_LINE_SIZE);
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dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
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}
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/*
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* Check if the link of a downstream PCIe port operates correctly.
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*
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* For that check if the optional Data Link Layer Link Active status gets
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* on within a 200ms period or failing that wait until the completion of
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* that period and check if link training has shown the completed status
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* continuously throughout the second half of that period.
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*
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* Observation with the ASMedia ASM2824 Gen 3 switch indicates it takes
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* 11-44ms to indicate the Data Link Layer Link Active status at 2.5GT/s,
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* though it may take a couple of link training iterations.
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*/
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static bool dm_pciauto_exp_link_stable(struct udevice *dev, int pcie_off)
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{
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u64 loops = 0, trcount = 0, ntrcount = 0, flips = 0;
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bool dllla, lnktr, plnktr;
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u16 exp_lnksta;
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pci_dev_t bdf;
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u64 end;
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dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA, &exp_lnksta);
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plnktr = !!(exp_lnksta & PCI_EXP_LNKSTA_LT);
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end = get_ticks() + usec_to_tick(200000);
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do {
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dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA,
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&exp_lnksta);
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dllla = !!(exp_lnksta & PCI_EXP_LNKSTA_DLLLA);
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lnktr = !!(exp_lnksta & PCI_EXP_LNKSTA_LT);
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flips += plnktr ^ lnktr;
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if (lnktr) {
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ntrcount = 0;
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trcount++;
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} else {
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ntrcount++;
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}
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loops++;
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plnktr = lnktr;
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} while (!dllla && get_ticks() < end);
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bdf = dm_pci_get_bdf(dev);
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debug("PCI Autoconfig: %02x.%02x.%02x: Fixup link: DL active: %u; "
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"%3llu flips, %6llu loops of which %6llu while training, "
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"final %6llu stable\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf),
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(unsigned int)dllla,
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(unsigned long long)flips, (unsigned long long)loops,
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(unsigned long long)trcount, (unsigned long long)ntrcount);
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return dllla || ntrcount >= loops / 2;
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}
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/*
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* Retrain the link of a downstream PCIe port by hand if necessary.
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*
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* This is needed at least where a downstream port of the ASMedia ASM2824
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* Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
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* Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
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* 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched
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* board.
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*
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* In such a configuration the switches are supposed to negotiate the link
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* speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link
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* continues switching between the two speeds indefinitely and the data
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* link layer never reaches the active state, with link training reported
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* repeatedly active ~84% of the time. Forcing the target link speed to
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* 2.5GT/s with the upstream ASM2824 device makes the two switches talk to
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* each other correctly however. And more interestingly retraining with a
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* higher target link speed afterwards lets the two successfully negotiate
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* 5.0GT/s.
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*
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* As this can potentially happen with any device and is cheap in the case
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* of correctly operating hardware, let's do it for all downstream ports,
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* for root complexes, PCIe switches and PCI/PCI-X to PCIe bridges.
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*
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* First check if automatic link training may have failed to complete, as
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* indicated by the optional Data Link Layer Link Active status being off
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* and the Link Bandwidth Management Status indicating that hardware has
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* changed the link speed or width in an attempt to correct unreliable
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* link operation. If this is the case, then check if the link operates
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* correctly by seeing whether it is being trained excessively. If it is,
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* then conclude the link is broken.
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*
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* In that case restrict the speed to 2.5GT/s, observing that the Target
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* Link Speed field is sticky and therefore the link will stay restricted
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* even after a device reset is later made by an OS that is unaware of the
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* problem. With the speed restricted request that the link be retrained
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* and check again if the link operates correctly. If not, then set the
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* Target Link Speed back to the original value.
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*
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* This requires the presence of the Link Control 2 register, so make sure
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* the PCI Express Capability Version is at least 2. Also don't try, for
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* obvious reasons, to limit the speed if 2.5GT/s is the only link speed
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* supported.
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*/
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static void dm_pciauto_exp_fixup_link(struct udevice *dev, int pcie_off)
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{
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u16 exp_lnksta, exp_lnkctl, exp_lnkctl2;
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u16 exp_flags, exp_type, exp_version;
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u32 exp_lnkcap;
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pci_dev_t bdf;
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dm_pci_read_config16(dev, pcie_off + PCI_EXP_FLAGS, &exp_flags);
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exp_version = exp_flags & PCI_EXP_FLAGS_VERS;
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if (exp_version < 2)
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return;
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exp_type = (exp_flags & PCI_EXP_FLAGS_TYPE) >> 4;
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switch (exp_type) {
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case PCI_EXP_TYPE_ROOT_PORT:
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case PCI_EXP_TYPE_DOWNSTREAM:
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case PCI_EXP_TYPE_PCIE_BRIDGE:
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break;
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default:
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return;
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}
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dm_pci_read_config32(dev, pcie_off + PCI_EXP_LNKCAP, &exp_lnkcap);
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if ((exp_lnkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
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return;
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dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA, &exp_lnksta);
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if ((exp_lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) !=
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PCI_EXP_LNKSTA_LBMS)
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return;
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if (dm_pciauto_exp_link_stable(dev, pcie_off))
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return;
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bdf = dm_pci_get_bdf(dev);
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printf("PCI Autoconfig: %02x.%02x.%02x: "
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"Downstream link non-functional\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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printf("PCI Autoconfig: %02x.%02x.%02x: "
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"Retrying with speed restricted to 2.5GT/s...\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKCTL, &exp_lnkctl);
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dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKCTL2, &exp_lnkctl2);
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dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL2,
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(exp_lnkctl2 & ~PCI_EXP_LNKCTL2_TLS) |
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PCI_EXP_LNKCTL2_TLS_2_5GT);
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dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL,
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exp_lnkctl | PCI_EXP_LNKCTL_RL);
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if (dm_pciauto_exp_link_stable(dev, pcie_off)) {
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printf("PCI Autoconfig: %02x.%02x.%02x: Succeeded!\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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} else {
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printf("PCI Autoconfig: %02x.%02x.%02x: Failed!\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL2,
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exp_lnkctl2);
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dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL,
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exp_lnkctl | PCI_EXP_LNKCTL_RL);
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}
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}
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void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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u16 cmdstat, prefechable_64;
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u8 io_32;
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
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int pcie_off;
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pci_mem = ctlr_hose->pci_mem;
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pci_prefetch = ctlr_hose->pci_prefetch;
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pci_io = ctlr_hose->pci_io;
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dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
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dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
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prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
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dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
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io_32 &= PCI_IO_RANGE_TYPE_MASK;
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/* Configure bus number registers */
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dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
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PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
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dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
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dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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/*
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* Set up memory and I/O filter limits, assume 32-bit
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* I/O space
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*/
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dm_pci_write_config16(dev, PCI_MEMORY_BASE,
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((pci_mem->bus_lower & 0xfff00000) >> 16) &
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PCI_MEMORY_RANGE_MASK);
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cmdstat |= PCI_COMMAND_MEMORY;
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}
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if (pci_prefetch) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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/*
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* Set up memory and I/O filter limits, assume 32-bit
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* I/O space
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*/
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
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(((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
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PCI_PREF_RANGE_MASK) | prefechable_64);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
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#ifdef CONFIG_SYS_PCI_64BIT
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dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
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pci_prefetch->bus_lower >> 32);
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#else
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dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
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#endif
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cmdstat |= PCI_COMMAND_MEMORY;
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} else {
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/* We don't support prefetchable memory for now, so disable */
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 |
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prefechable_64);
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
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prefechable_64);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
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dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
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dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
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}
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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dm_pci_write_config8(dev, PCI_IO_BASE,
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(((pci_io->bus_lower & 0x0000f000) >> 8) &
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PCI_IO_RANGE_MASK) | io_32);
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if (io_32 == PCI_IO_RANGE_TYPE_32)
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dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
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(pci_io->bus_lower & 0xffff0000) >> 16);
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cmdstat |= PCI_COMMAND_IO;
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} else {
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/* Disable I/O if unsupported */
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dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32);
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dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32);
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if (io_32 == PCI_IO_RANGE_TYPE_32) {
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dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0);
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dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0);
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}
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}
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/* For PCIe devices see if we need to retrain the link by hand */
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pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (pcie_off)
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dm_pciauto_exp_fixup_link(dev, pcie_off);
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/* Enable memory and I/O accesses, enable bus master */
|
|
dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
|
|
}
|
|
|
|
void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
|
|
{
|
|
struct pci_region *pci_mem;
|
|
struct pci_region *pci_prefetch;
|
|
struct pci_region *pci_io;
|
|
struct udevice *ctlr = pci_get_controller(dev);
|
|
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
|
|
|
|
pci_mem = ctlr_hose->pci_mem;
|
|
pci_prefetch = ctlr_hose->pci_prefetch;
|
|
pci_io = ctlr_hose->pci_io;
|
|
|
|
/* Configure bus number registers */
|
|
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
|
|
|
|
if (pci_mem) {
|
|
/* Round memory allocator to 1MB boundary */
|
|
pciauto_region_align(pci_mem, 0x100000);
|
|
|
|
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
|
|
((pci_mem->bus_lower - 1) >> 16) &
|
|
PCI_MEMORY_RANGE_MASK);
|
|
}
|
|
|
|
if (pci_prefetch) {
|
|
u16 prefechable_64;
|
|
|
|
dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
|
|
&prefechable_64);
|
|
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
|
|
|
|
/* Round memory allocator to 1MB boundary */
|
|
pciauto_region_align(pci_prefetch, 0x100000);
|
|
|
|
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
|
|
(((pci_prefetch->bus_lower - 1) >> 16) &
|
|
PCI_PREF_RANGE_MASK) | prefechable_64);
|
|
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
|
|
#ifdef CONFIG_SYS_PCI_64BIT
|
|
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
|
|
(pci_prefetch->bus_lower - 1) >> 32);
|
|
#else
|
|
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
|
|
#endif
|
|
}
|
|
|
|
if (pci_io) {
|
|
u8 io_32;
|
|
|
|
dm_pci_read_config8(dev, PCI_IO_LIMIT,
|
|
&io_32);
|
|
io_32 &= PCI_IO_RANGE_TYPE_MASK;
|
|
|
|
/* Round I/O allocator to 4KB boundary */
|
|
pciauto_region_align(pci_io, 0x1000);
|
|
|
|
dm_pci_write_config8(dev, PCI_IO_LIMIT,
|
|
((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
|
|
PCI_IO_RANGE_MASK) | io_32);
|
|
if (io_32 == PCI_IO_RANGE_TYPE_32)
|
|
dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
|
|
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* HJF: Changed this to return int. I think this is required
|
|
* to get the correct result when scanning bridges
|
|
*/
|
|
int dm_pciauto_config_device(struct udevice *dev)
|
|
{
|
|
struct pci_region *pci_mem;
|
|
struct pci_region *pci_prefetch;
|
|
struct pci_region *pci_io;
|
|
unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
|
|
unsigned short class;
|
|
struct udevice *ctlr = pci_get_controller(dev);
|
|
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
|
|
int ret;
|
|
|
|
pci_mem = ctlr_hose->pci_mem;
|
|
pci_prefetch = ctlr_hose->pci_prefetch;
|
|
pci_io = ctlr_hose->pci_io;
|
|
|
|
dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
|
|
|
|
switch (class) {
|
|
case PCI_CLASS_BRIDGE_PCI:
|
|
debug("PCI Autoconfig: Found P2P bridge, device %d\n",
|
|
PCI_DEV(dm_pci_get_bdf(dev)));
|
|
|
|
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
|
|
|
|
ret = dm_pci_hose_probe_bus(dev);
|
|
if (ret < 0)
|
|
return log_msg_ret("probe", ret);
|
|
sub_bus = ret;
|
|
break;
|
|
|
|
case PCI_CLASS_BRIDGE_CARDBUS:
|
|
/*
|
|
* just do a minimal setup of the bridge,
|
|
* let the OS take care of the rest
|
|
*/
|
|
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
|
|
|
|
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
|
|
PCI_DEV(dm_pci_get_bdf(dev)));
|
|
|
|
break;
|
|
|
|
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
|
|
case PCI_CLASS_BRIDGE_OTHER:
|
|
debug("PCI Autoconfig: Skipping bridge device %d\n",
|
|
PCI_DEV(dm_pci_get_bdf(dev)));
|
|
break;
|
|
#endif
|
|
#if defined(CONFIG_ARCH_MPC834X)
|
|
case PCI_CLASS_BRIDGE_OTHER:
|
|
/*
|
|
* The host/PCI bridge 1 seems broken in 8349 - it presents
|
|
* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
|
|
* device claiming resources io/mem/irq.. we only allow for
|
|
* the PIMMR window to be allocated (BAR0 - 1MB size)
|
|
*/
|
|
debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
|
|
dm_pciauto_setup_device(dev, 0, hose->pci_mem,
|
|
hose->pci_prefetch, hose->pci_io);
|
|
break;
|
|
#endif
|
|
|
|
case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
|
|
debug("PCI AutoConfig: Found PowerPC device\n");
|
|
/* fall through */
|
|
|
|
default:
|
|
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
|
|
break;
|
|
}
|
|
|
|
return sub_bus;
|
|
}
|