114 lines
1.8 KiB
Plaintext
114 lines
1.8 KiB
Plaintext
/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "socfpga_cyclone5.dtsi"
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/ {
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model = "samtec VIN|ING FPGA";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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aliases {
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ethernet0 = &gmac1;
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udc0 = &usb0;
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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rxd0-skew-ps = <0>;
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rxd1-skew-ps = <0>;
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rxd2-skew-ps = <0>;
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rxd3-skew-ps = <0>;
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txen-skew-ps = <0>;
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txc-skew-ps = <2600>;
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rxdv-skew-ps = <0>;
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rxc-skew-ps = <2000>;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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rtc: rtc@68 {
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compatible = "stm,m41t82";
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reg = <0x68>;
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};
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};
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&qspi {
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status = "okay";
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u-boot,dm-pre-reloc;
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flash0: n25q128@0 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128", "spi-flash";
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reg = <0>; /* chip select */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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page-size = <256>;
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block-size = <16>; /* 2^16, 64KB */
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read-delay = <4>; /* delay value in read data capture register */
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tshsl-ns = <50>;
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tsd2d-ns = <50>;
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tchsh-ns = <4>;
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tslch-ns = <4>;
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};
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flash1: n25q00@1 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00", "spi-flash";
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reg = <1>; /* chip select */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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page-size = <256>;
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block-size = <16>; /* 2^16, 64KB */
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read-delay = <4>; /* delay value in read data capture register */
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tshsl-ns = <50>;
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tsd2d-ns = <50>;
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tchsh-ns = <4>;
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tslch-ns = <4>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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