99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/*
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8m_ddr.h>
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#include <asm/arch/sys_proto.h>
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void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
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{
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int i = 0;
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for (i = 0; i < num; i++) {
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reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
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ddrc_cfg++;
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}
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}
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void ddr_init(struct dram_timing_info *dram_timing)
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{
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volatile unsigned int tmp_t;
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); /* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* deassert [4]src_system_rst_b! */
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/* change the clock source of dram_apb_clk_root */
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clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); /* to source 4 --800MHz/4 */
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dram_pll_init(DRAM_PLL_OUT_600M);
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reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
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reg32setbit(0x303A00F8,5); /* PU_PGC_SW_PUP_REQ */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
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reg32_write(DDRC_DBG1(0), 0x00000001);
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reg32_write(DDRC_PWRCTL(0), 0x00000001);
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while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
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;
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/* config the uMCTL2's registers */
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ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
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reg32_write(DDRC_RFSHCTL3(0), 0x00000001);
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/* RESET: <ctn> DEASSERTED */
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/* RESET: <a Port 0 DEASSERTED(0) */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
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reg32_write(DDRC_DBG1(0), 0x00000000);
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reg32_write(DDRC_PWRCTL(0), 0x00000aa);
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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reg32_write(DDRC_DFIMISC(0), 0x00000000);
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/* config the DDR PHY's registers */
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ddr_cfg_phy(dram_timing);
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do {
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tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*0x00020097);
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} while (tmp_t != 0);
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reg32_write(DDRC_DFIMISC(0), 0x00000020);
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/* wait DFISTAT.dfi_init_complete to 1 */
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while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
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;
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/* clear DFIMISC.dfi_init_complete_en */
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reg32_write(DDRC_DFIMISC(0), 0x00000000);
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/* set DFIMISC.dfi_init_complete_en again */
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reg32_write(DDRC_DFIMISC(0), 0x00000001);
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reg32_write(DDRC_PWRCTL(0), 0x0000088);
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/* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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/* wait SWSTAT.sw_done_ack to 1 */
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while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
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;
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/* wait STAT to normal state */
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while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
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;
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reg32_write(DDRC_PWRCTL(0), 0x0000088);
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reg32_write(DDRC_PCTRL_0(0), 0x00000001);
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reg32_write(DDRC_RFSHCTL3(0), 0x00000000); /* dis_auto-refresh is set to 0 */
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/* save the dram timing config into memory */
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dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
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}
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