540 lines
17 KiB
C
540 lines
17 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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/* Design Guidelines parameters */
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u32 g_zpri_data = 123; /* controller data - P drive strength */
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u32 g_znri_data = 123; /* controller data - N drive strength */
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u32 g_zpri_ctrl = 74; /* controller C/A - P drive strength */
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u32 g_znri_ctrl = 74; /* controller C/A - N drive strength */
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u32 g_zpodt_data = 45; /* controller data - P ODT */
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u32 g_znodt_data = 45; /* controller data - N ODT */
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u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
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u32 g_znodt_ctrl = 45; /* controller data - N ODT */
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u32 g_odt_config_2cs = 0x120012;
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u32 g_odt_config_1cs = 0x10000;
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u32 g_rtt_nom = 0x44;
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u32 g_dic = 0x2;
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#ifdef STATIC_ALGO_SUPPORT
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#define PARAM_NOT_CARE 0
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#define MAX_STATIC_SEQ 48
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u32 silicon_delay[HWS_MAX_DEVICE_NUM];
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struct hws_tip_static_config_info static_config[HWS_MAX_DEVICE_NUM];
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static reg_data *static_init_controller_config[HWS_MAX_DEVICE_NUM];
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/* debug delay in write leveling */
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int wl_debug_delay = 0;
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/* pup register #3 for functional board */
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int function_reg_value = 8;
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u32 silicon;
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u32 read_ready_delay_phase_offset[] = { 4, 4, 4, 4, 6, 6, 6, 6 };
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static struct cs_element chip_select_map[] = {
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/* CS Value (single only) Num_CS */
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{0, 0},
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{0, 1},
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{1, 1},
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{0, 2},
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{2, 1},
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{0, 2},
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{0, 2},
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{0, 3},
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{3, 1},
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{0, 2},
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{0, 2},
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{0, 3},
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{0, 2},
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{0, 3},
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{0, 3},
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{0, 4}
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};
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/*
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* Register static init controller DB
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*/
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int ddr3_tip_init_specific_reg_config(u32 dev_num, reg_data *reg_config_arr)
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{
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static_init_controller_config[dev_num] = reg_config_arr;
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return MV_OK;
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}
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/*
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* Register static info DB
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*/
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int ddr3_tip_init_static_config_db(
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u32 dev_num, struct hws_tip_static_config_info *static_config_info)
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{
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static_config[dev_num].board_trace_arr =
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static_config_info->board_trace_arr;
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static_config[dev_num].package_trace_arr =
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static_config_info->package_trace_arr;
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silicon_delay[dev_num] = static_config_info->silicon_delay;
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return MV_OK;
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}
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/*
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* Static round trip flow - Calculates the total round trip delay.
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*/
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int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
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struct trip_delay_element *table_ptr,
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int is_wl, u32 *round_trip_delay_arr)
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{
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u32 bus_index, global_bus;
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u32 if_id;
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u32 bus_per_interface;
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int sign;
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u32 temp;
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u32 board_trace;
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struct trip_delay_element *pkg_delay_ptr;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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/*
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* In WL we calc the diff between Clock to DQs in RL we sum the round
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* trip of Clock and DQs
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*/
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sign = (is_wl) ? -1 : 1;
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bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES();
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for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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for (bus_index = 0; bus_index < bus_per_interface;
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bus_index++) {
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VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
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global_bus = (if_id * bus_per_interface) + bus_index;
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/* calculate total trip delay (package and board) */
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board_trace = (table_ptr[global_bus].dqs_delay * sign) +
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table_ptr[global_bus].ck_delay;
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temp = (board_trace * 163) / 1000;
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/* Convert the length to delay in psec units */
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pkg_delay_ptr =
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static_config[dev_num].package_trace_arr;
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round_trip_delay_arr[global_bus] = temp +
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(int)(pkg_delay_ptr[global_bus].dqs_delay *
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sign) +
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(int)pkg_delay_ptr[global_bus].ck_delay +
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(int)((is_wl == 1) ? wl_debug_delay :
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(int)silicon_delay[dev_num]);
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_TRACE,
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("Round Trip Build round_trip_delay_arr[0x%x]: 0x%x temp 0x%x\n",
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global_bus, round_trip_delay_arr[global_bus],
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temp));
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}
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}
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return MV_OK;
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}
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/*
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* Write leveling for static flow - calculating the round trip delay of the
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* DQS signal.
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*/
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int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
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enum hws_ddr_freq frequency,
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u32 *round_trip_delay_arr)
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{
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u32 bus_index; /* index to the bus loop */
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u32 bus_start_index;
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u32 bus_per_interface;
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u32 phase = 0;
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u32 adll = 0, adll_cen, adll_inv, adll_final;
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u32 adll_period = MEGA / freq_val[frequency] / 64;
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("ddr3_tip_write_leveling_static_config\n"));
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_TRACE,
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("dev_num 0x%x IF 0x%x freq %d (adll_period 0x%x)\n",
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dev_num, if_id, frequency, adll_period));
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bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES();
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bus_start_index = if_id * bus_per_interface;
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for (bus_index = bus_start_index;
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bus_index < (bus_start_index + bus_per_interface); bus_index++) {
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VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
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phase = round_trip_delay_arr[bus_index] / (32 * adll_period);
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adll = (round_trip_delay_arr[bus_index] -
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(phase * 32 * adll_period)) / adll_period;
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adll = (adll > 31) ? 31 : adll;
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adll_cen = 16 + adll;
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adll_inv = adll_cen / 32;
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adll_final = adll_cen - (adll_inv * 32);
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adll_final = (adll_final > 31) ? 31 : adll_final;
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("\t%d - phase 0x%x adll 0x%x\n",
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bus_index, phase, adll));
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/*
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* Writing to all 4 phy of Interface number,
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* bit 0 \96 4 \96 ADLL, bit 6-8 phase
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*/
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CHECK_STATUS(ddr3_tip_bus_read_modify_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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(bus_index % 4), DDR_PHY_DATA,
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PHY_WRITE_DELAY(cs),
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((phase << 6) + (adll & 0x1f)), 0x1df));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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ACCESS_TYPE_UNICAST, (bus_index % 4),
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DDR_PHY_DATA, WRITE_CENTRALIZATION_PHY_REG,
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((adll_inv & 0x1) << 5) + adll_final));
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}
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return MV_OK;
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}
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/*
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* Read leveling for static flow
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*/
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int ddr3_tip_read_leveling_static_config(u32 dev_num,
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u32 if_id,
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enum hws_ddr_freq frequency,
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u32 *total_round_trip_delay_arr)
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{
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u32 cs, data0, data1, data3 = 0;
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u32 bus_index; /* index to the bus loop */
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u32 bus_start_index;
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u32 phase0, phase1, max_phase;
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u32 adll0, adll1;
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u32 cl_value;
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u32 min_delay;
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u32 sdr_period = MEGA / freq_val[frequency];
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u32 ddr_period = MEGA / freq_val[frequency] / 2;
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u32 adll_period = MEGA / freq_val[frequency] / 64;
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enum hws_speed_bin speed_bin_index;
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u32 rd_sample_dly[MAX_CS_NUM] = { 0 };
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u32 rd_ready_del[MAX_CS_NUM] = { 0 };
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u32 bus_per_interface = GET_TOPOLOGY_NUM_OF_BUSES();
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struct hws_topology_map *tm = ddr3_get_topology_map();
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("ddr3_tip_read_leveling_static_config\n"));
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("dev_num 0x%x ifc 0x%x freq %d\n", dev_num,
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if_id, frequency));
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_TRACE,
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("Sdr_period 0x%x Ddr_period 0x%x adll_period 0x%x\n",
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sdr_period, ddr_period, adll_period));
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if (tm->interface_params[first_active_if].memory_freq ==
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frequency) {
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cl_value = tm->interface_params[first_active_if].cas_l;
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("cl_value 0x%x\n", cl_value));
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} else {
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speed_bin_index = tm->interface_params[if_id].speed_bin_index;
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cl_value = cas_latency_table[speed_bin_index].cl_val[frequency];
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("cl_value 0x%x speed_bin_index %d\n",
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cl_value, speed_bin_index));
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}
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bus_start_index = if_id * bus_per_interface;
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for (bus_index = bus_start_index;
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bus_index < (bus_start_index + bus_per_interface);
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bus_index += 2) {
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VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
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cs = chip_select_map[
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tm->interface_params[if_id].as_bus_params[
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(bus_index % 4)].cs_bitmask].cs_num;
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/* read sample delay calculation */
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min_delay = (total_round_trip_delay_arr[bus_index] <
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total_round_trip_delay_arr[bus_index + 1]) ?
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total_round_trip_delay_arr[bus_index] :
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total_round_trip_delay_arr[bus_index + 1];
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/* round down */
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rd_sample_dly[cs] = 2 * (min_delay / (sdr_period * 2));
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_TRACE,
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("\t%d - min_delay 0x%x cs 0x%x rd_sample_dly[cs] 0x%x\n",
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bus_index, min_delay, cs, rd_sample_dly[cs]));
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/* phase calculation */
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phase0 = (total_round_trip_delay_arr[bus_index] -
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(sdr_period * rd_sample_dly[cs])) / (ddr_period);
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phase1 = (total_round_trip_delay_arr[bus_index + 1] -
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(sdr_period * rd_sample_dly[cs])) / (ddr_period);
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max_phase = (phase0 > phase1) ? phase0 : phase1;
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_TRACE,
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("\tphase0 0x%x phase1 0x%x max_phase 0x%x\n",
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phase0, phase1, max_phase));
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/* ADLL calculation */
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adll0 = (u32)((total_round_trip_delay_arr[bus_index] -
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(sdr_period * rd_sample_dly[cs]) -
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(ddr_period * phase0)) / adll_period);
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adll0 = (adll0 > 31) ? 31 : adll0;
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adll1 = (u32)((total_round_trip_delay_arr[bus_index + 1] -
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(sdr_period * rd_sample_dly[cs]) -
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(ddr_period * phase1)) / adll_period);
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adll1 = (adll1 > 31) ? 31 : adll1;
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/* The Read delay close the Read FIFO */
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rd_ready_del[cs] = rd_sample_dly[cs] +
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read_ready_delay_phase_offset[max_phase];
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_TRACE,
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("\tadll0 0x%x adll1 0x%x rd_ready_del[cs] 0x%x\n",
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adll0, adll1, rd_ready_del[cs]));
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/*
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* Write to the phy of Interface (bit 0 \96 4 \96 ADLL,
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* bit 6-8 phase)
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*/
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data0 = ((phase0 << 6) + (adll0 & 0x1f));
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data1 = ((phase1 << 6) + (adll1 & 0x1f));
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CHECK_STATUS(ddr3_tip_bus_read_modify_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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(bus_index % 4), DDR_PHY_DATA, PHY_READ_DELAY(cs),
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data0, 0x1df));
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CHECK_STATUS(ddr3_tip_bus_read_modify_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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((bus_index + 1) % 4), DDR_PHY_DATA,
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PHY_READ_DELAY(cs), data1, 0x1df));
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}
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for (bus_index = 0; bus_index < bus_per_interface; bus_index++) {
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VALIDATE_ACTIVE(tm->bus_act_mask, bus_index);
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CHECK_STATUS(ddr3_tip_bus_read_modify_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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bus_index, DDR_PHY_DATA, 0x3, data3, 0x1f));
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}
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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READ_DATA_SAMPLE_DELAY,
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(rd_sample_dly[0] + cl_value) + (rd_sample_dly[1] << 8),
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MASK_ALL_BITS));
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/* Read_ready_del0 bit 0-4 , CS bits 8-12 */
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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READ_DATA_READY_DELAY,
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rd_ready_del[0] + (rd_ready_del[1] << 8) + cl_value,
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MASK_ALL_BITS));
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return MV_OK;
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}
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/*
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* DDR3 Static flow
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*/
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int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq)
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{
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u32 if_id = 0;
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struct trip_delay_element *table_ptr;
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u32 wl_total_round_trip_delay_arr[MAX_TOTAL_BUS_NUM];
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u32 rl_total_round_trip_delay_arr[MAX_TOTAL_BUS_NUM];
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struct init_cntr_param init_cntr_prm;
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int ret;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("ddr3_tip_run_static_alg"));
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init_cntr_prm.do_mrs_phy = 1;
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init_cntr_prm.is_ctrl64_bit = 0;
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init_cntr_prm.init_phy = 1;
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ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
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if (ret != MV_OK) {
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DEBUG_TRAINING_STATIC_IP(
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DEBUG_LEVEL_ERROR,
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("hws_ddr3_tip_init_controller failure\n"));
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}
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/* calculate the round trip delay for Write Leveling */
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table_ptr = static_config[dev_num].board_trace_arr;
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CHECK_STATUS(ddr3_tip_static_round_trip_arr_build
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(dev_num, table_ptr, 1,
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wl_total_round_trip_delay_arr));
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/* calculate the round trip delay for Read Leveling */
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CHECK_STATUS(ddr3_tip_static_round_trip_arr_build
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(dev_num, table_ptr, 0,
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rl_total_round_trip_delay_arr));
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for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
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/* check if the interface is enabled */
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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/*
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* Static frequency is defined according to init-frequency
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* (not target)
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*/
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("Static IF %d freq %d\n",
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if_id, freq));
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CHECK_STATUS(ddr3_tip_write_leveling_static_config
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(dev_num, if_id, freq,
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wl_total_round_trip_delay_arr));
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CHECK_STATUS(ddr3_tip_read_leveling_static_config
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(dev_num, if_id, freq,
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rl_total_round_trip_delay_arr));
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}
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return MV_OK;
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}
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/*
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* Init controller for static flow
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*/
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int ddr3_tip_static_init_controller(u32 dev_num)
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{
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u32 index_cnt = 0;
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("ddr3_tip_static_init_controller\n"));
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while (static_init_controller_config[dev_num][index_cnt].reg_addr !=
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0) {
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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static_init_controller_config[dev_num][index_cnt].
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reg_addr,
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static_init_controller_config[dev_num][index_cnt].
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reg_data,
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static_init_controller_config[dev_num][index_cnt].
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reg_mask));
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("Init_controller index_cnt %d\n",
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index_cnt));
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index_cnt++;
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}
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return MV_OK;
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}
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int ddr3_tip_static_phy_init_controller(u32 dev_num)
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{
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("Phy Init Controller 2\n"));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa4,
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0x3dfe));
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DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
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("Phy Init Controller 3\n"));
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CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa6,
|
|
0xcb2));
|
|
|
|
DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
|
|
("Phy Init Controller 4\n"));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa9,
|
|
0));
|
|
|
|
DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
|
|
("Static Receiver Calibration\n"));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xd0,
|
|
0x1f));
|
|
|
|
DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE,
|
|
("Static V-REF Calibration\n"));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xa8,
|
|
0x434));
|
|
|
|
return MV_OK;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Configure phy (called by static init controller) for static flow
|
|
*/
|
|
int ddr3_tip_configure_phy(u32 dev_num)
|
|
{
|
|
u32 if_id, phy_id;
|
|
struct hws_topology_map *tm = ddr3_get_topology_map();
|
|
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
|
|
PAD_ZRI_CALIB_PHY_REG,
|
|
((0x7f & g_zpri_data) << 7 | (0x7f & g_znri_data))));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
|
|
PAD_ZRI_CALIB_PHY_REG,
|
|
((0x7f & g_zpri_ctrl) << 7 | (0x7f & g_znri_ctrl))));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
|
|
PAD_ODT_CALIB_PHY_REG,
|
|
((0x3f & g_zpodt_data) << 6 | (0x3f & g_znodt_data))));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
|
|
PAD_ODT_CALIB_PHY_REG,
|
|
((0x3f & g_zpodt_ctrl) << 6 | (0x3f & g_znodt_ctrl))));
|
|
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
|
|
PAD_PRE_DISABLE_PHY_REG, 0));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
|
|
CMOS_CONFIG_PHY_REG, 0));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
|
|
CMOS_CONFIG_PHY_REG, 0));
|
|
|
|
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
|
|
/* check if the interface is enabled */
|
|
VALIDATE_ACTIVE(tm->if_act_mask, if_id);
|
|
|
|
for (phy_id = 0;
|
|
phy_id < tm->num_of_bus_per_interface;
|
|
phy_id++) {
|
|
VALIDATE_ACTIVE(tm->bus_act_mask, phy_id);
|
|
/* Vref & clamp */
|
|
CHECK_STATUS(ddr3_tip_bus_read_modify_write
|
|
(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, phy_id, DDR_PHY_DATA,
|
|
PAD_CONFIG_PHY_REG,
|
|
((clamp_tbl[if_id] << 4) | vref),
|
|
((0x7 << 4) | 0x7)));
|
|
/* clamp not relevant for control */
|
|
CHECK_STATUS(ddr3_tip_bus_read_modify_write
|
|
(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, phy_id, DDR_PHY_CONTROL,
|
|
PAD_CONFIG_PHY_REG, 0x4, 0x7));
|
|
}
|
|
}
|
|
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
|
|
ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0x90,
|
|
0x6002));
|
|
|
|
return MV_OK;
|
|
}
|