167 lines
5.8 KiB
Plaintext
167 lines
5.8 KiB
Plaintext
External Debug Support
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----------------------
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Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
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restrictions on external debugging (JTAG). In particular, for the debugger to
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be able to receive control after a single step or breakpoint:
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- MSR[DE] must be set
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- A valid opcode must be fetchable, through the MMU, from the debug
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exception vector (IVPR + IVOR15).
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To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
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immediately on entry and keeps it set. It also uses a temporary TLB to keep a
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mapping to a valid opcode at the debug exception vector, even if we normally
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don't support exception vectors being used that early, and that's not the area
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where U-Boot currently executes from.
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Note that there may still be some small windows where debugging will not work,
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such as in between updating IVPR and IVOR15.
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Config Switches:
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----------------
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Please refer README section "MPC85xx External Debug Support"
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Major Config Switches during various boot Modes
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----------------------------------------------
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NOR boot
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!defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
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NOR boot Secure
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!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
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RAMBOOT(SD, SPI & NAND boot)
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defined(CONFIG_SYS_RAMBOOT)
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RAMBOOT Secure (SD, SPI & NAND)
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defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
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NAND SPL BOOT
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defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
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TLB Entries during u-boot execution
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-----------------------------------
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Note: Sequence number is in order of execution
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A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
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1) TLB entry to overcome e500 v1/v2 debug restriction
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Location : Label "_start"
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TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
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EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
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Properties : 256K, AS0, I, IPROT
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2) TLB entry for working in AS1
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Location : Label "create_init_ram_area"
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TLB Entry : 15
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EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
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Properties : 1M, AS1, I, G, IPROT
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3) TLB entry for the stack during AS1
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Location : Lable "create_init_ram_area"
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TLB Entry : 14
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EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
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Properties : 16K, AS1, IPROT
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4) TLB entry for CCSRBAR during AS1 execution
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Location : cpu_init_early_f
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TLB Entry : 13
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EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
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Properties : 1M, AS1, I, G
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5) Invalidate unproctected TLB Entries
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Location : cpu_init_early_f
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Invalidated: 13
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6) Create TLB entries as per boards/freescale/<board>/tlb.c
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Location : cpu_init_early_f --> init_tlbs()
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Properties : ..., AS0, ...
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Please note It can overwrites previous TLB Entries.
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7) Disable TLB Entries of AS1
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Location : cpu_init_f --> disable_tlb()
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Disable : 15, 14
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8) Update Flash's TLB entry
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Location : Board_init_r
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TLB entry : Search from TLB entries
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EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
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Properties : Board specific size, AS0, I, G, IPROT
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B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
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1) TLB entry to overcome e500 v1/v2 debug restriction
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Location : Label "_start"
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TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
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#if defined(CONFIG_NXP_ESBC)
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EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
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Properties : 1M, AS1, I, G, IPROT
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#else
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EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
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Properties : 4M, AS0, I, G, IPROT
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#endif
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2) TLB entry for working in AS1
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Location : Label "create_init_ram_area"
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TLB Entry : 15
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#if defined(CONFIG_NXP_ESBC)
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EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
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Properties : 1M, AS1, I, G, IPROT
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#else
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EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
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Properties : 4M, AS1, I, G, IPROT
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#endif
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3) TLB entry for the stack during AS1
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Location : Lable "create_init_ram_area"
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TLB Entry : 14
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EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
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Properties : 16K, AS1, IPROT
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4) TLB entry for CCSRBAR during AS1 execution
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Location : cpu_init_early_f
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TLB Entry : 13
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EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
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Properties : 1M, AS1, I, G
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5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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Location : cpu_init_early_f
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TLB Entry : 9
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EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
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Properties : 1M, AS1, I
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6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
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Location : cpu_init_early_f --> setup_ifc
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TLB Entry : Get Flash TLB
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EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
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Properties : 4M, AS1, I, G, IPROT
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7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
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Location : cpu_init_early_f --> setup_ifc
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TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
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EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
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Properties : 4M, AS0, I, G, IPROT
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8) Invalidate unproctected TLB Entries
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Location : cpu_init_early_f
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Invalidated: 13, 9
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9) Create TLB entries as per boards/freescale/<board>/tlb.c
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Location : cpu_init_early_f --> init_tlbs()
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Properties : ..., AS0, ...
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Note: It can overwrites previous TLB Entries
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10) Disable TLB Entries of AS1
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Location : cpu_init_f --> disable_tlb()
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Disable : 15, 14
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11) Create DDR's TLB entriy
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Location : Board_init_f -> dram_init
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TLB entry : Search free TLB entry
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12) Update Flash's TLB entry
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Location : Board_init_r
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TLB entry : Search from TLB entries
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EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
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Properties : Board specific size, AS0, I, G, IPROT
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