381 lines
8.9 KiB
Plaintext
381 lines
8.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp13-clks.h>
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#include <dt-bindings/reset/stm32mp13-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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firmware {
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optee {
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method = "smc";
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compatible = "linaro,optee-tz";
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};
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scmi: scmi {
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compatible = "linaro,scmi-optee";
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#address-cells = <1>;
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#size-cells = <0>;
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linaro,optee-channel-id = <0>;
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shmem = <&scmi_shm>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&intc>;
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always-on;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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scmi_sram: sram@2ffff000 {
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compatible = "mmio-sram";
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reg = <0x2ffff000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2ffff000 0x1000>;
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scmi_shm: scmi-sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0 0x80>;
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};
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART4_K>;
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resets = <&rcc UART4_R>;
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status = "disabled";
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};
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dma1: dma-controller@48000000 {
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compatible = "st,stm32-dma";
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reg = <0x48000000 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc DMA1>;
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resets = <&rcc DMA1_R>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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};
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dma2: dma-controller@48001000 {
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compatible = "st,stm32-dma";
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reg = <0x48001000 0x400>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc DMA2>;
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resets = <&rcc DMA2_R>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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};
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dmamux1: dma-router@48002000 {
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compatible = "st,stm32h7-dmamux";
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reg = <0x48002000 0x40>;
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clocks = <&rcc DMAMUX1>;
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resets = <&rcc DMAMUX1_R>;
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#dma-cells = <3>;
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dma-masters = <&dma1 &dma2>;
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dma-requests = <128>;
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dma-channels = <16>;
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp13-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp13-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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mdma: dma-controller@58000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x58000000 0x1000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc MDMA>;
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#dma-cells = <5>;
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dma-channels = <32>;
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dma-requests = <48>;
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};
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sdmmc1: mmc@58005000 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x20253180>;
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc SDMMC1_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <130000000>;
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status = "disabled";
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};
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sdmmc2: mmc@58007000 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x20253180>;
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reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc SDMMC2_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <130000000>;
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status = "disabled";
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};
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iwdg2: watchdog@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scmi_clk CK_SCMI_RTCAPB>,
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<&scmi_clk CK_SCMI_RTC>;
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clock-names = "pclk", "rtc_ck";
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status = "disabled";
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};
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bsec: efuse@5c005000 {
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compatible = "st,stm32mp13-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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part_number_otp: part_number_otp@4 {
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reg = <0x4 0x2>;
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};
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ts_cal1: calib@5c {
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reg = <0x5c 0x2>;
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};
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ts_cal2: calib@5e {
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reg = <0x5e 0x2>;
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};
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};
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/*
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* Break node order to solve dependency probe issue between
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* pinctrl and exti.
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*/
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pinctrl: pinctrl@50002000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp135-pinctrl";
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ranges = <0 0x50002000 0x8400>;
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interrupt-parent = <&exti>;
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st,syscfg = <&exti 0x60 0xff>;
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pins-are-numbered;
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gpioa: gpio@50002000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc GPIOA>;
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st,bank-name = "GPIOA";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 0 16>;
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};
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gpiob: gpio@50003000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc GPIOB>;
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st,bank-name = "GPIOB";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 16 16>;
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};
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gpioc: gpio@50004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc GPIOC>;
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st,bank-name = "GPIOC";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 32 16>;
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};
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gpiod: gpio@50005000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x400>;
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clocks = <&rcc GPIOD>;
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st,bank-name = "GPIOD";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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gpioe: gpio@50006000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x400>;
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clocks = <&rcc GPIOE>;
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st,bank-name = "GPIOE";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 64 16>;
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};
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gpiof: gpio@50007000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x400>;
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clocks = <&rcc GPIOF>;
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st,bank-name = "GPIOF";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 80 16>;
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};
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gpiog: gpio@50008000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x400>;
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clocks = <&rcc GPIOG>;
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st,bank-name = "GPIOG";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 96 16>;
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};
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gpioh: gpio@50009000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x7000 0x400>;
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clocks = <&rcc GPIOH>;
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st,bank-name = "GPIOH";
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ngpios = <15>;
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gpio-ranges = <&pinctrl 0 112 15>;
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};
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gpioi: gpio@5000a000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x8000 0x400>;
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clocks = <&rcc GPIOI>;
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st,bank-name = "GPIOI";
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ngpios = <8>;
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gpio-ranges = <&pinctrl 0 128 8>;
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};
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};
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};
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};
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