162 lines
2.5 KiB
C
162 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2021 NXP
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*/
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#ifndef _ASM_ARCH_CGC_H
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#define _ASM_ARCH_CGC_H
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enum cgc_clk {
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DUMMY0_CLK,
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DUMMY1_CLK,
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LPOSC,
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NIC_APCLK,
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NIC_PERCLK,
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XBAR_APCLK,
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XBAR_BUSCLK,
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AD_SLOWCLK,
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SOSC,
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SOSC_DIV1,
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SOSC_DIV2,
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SOSC_DIV3,
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FRO,
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FRO_DIV1,
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FRO_DIV2,
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FRO_DIV3,
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PLL2,
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PLL3,
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PLL3_VCODIV,
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PLL3_PFD0,
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PLL3_PFD1,
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PLL3_PFD2,
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PLL3_PFD3,
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PLL3_PFD0_DIV1,
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PLL3_PFD0_DIV2,
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PLL3_PFD1_DIV1,
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PLL3_PFD1_DIV2,
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PLL3_PFD2_DIV1,
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PLL3_PFD2_DIV2,
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PLL3_PFD3_DIV1,
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PLL3_PFD3_DIV2,
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LVDS,
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LPAV_AXICLK,
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LPAV_AHBCLK,
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LPAV_BUSCLK,
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PLL4,
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PLL4_VCODIV,
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PLL4_PFD0,
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PLL4_PFD1,
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PLL4_PFD2,
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PLL4_PFD3,
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PLL4_PFD0_DIV1,
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PLL4_PFD0_DIV2,
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PLL4_PFD1_DIV1,
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PLL4_PFD1_DIV2,
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PLL4_PFD2_DIV1,
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PLL4_PFD2_DIV2,
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PLL4_PFD3_DIV1,
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PLL4_PFD3_DIV2,
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CM33_BUSCLK,
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PLL1_VCO_DIV,
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PLL0_PFD2_DIV,
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PLL0_PFD1_DIV,
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};
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struct cgc1_regs {
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u32 verid;
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u32 rsvd1[4];
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u32 ca35clk;
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u32 rsvd2[2];
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u32 clkoutcfg;
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u32 rsvd3[4];
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u32 nicclk;
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u32 xbarclk;
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u32 rsvd4[21];
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u32 clkdivrst;
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u32 rsvd5[29];
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u32 soscdiv;
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u32 rsvd6[63];
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u32 frodiv;
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u32 rsvd7[189];
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u32 pll2csr;
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u32 rsvd8[3];
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u32 pll2cfg;
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u32 rsvd9;
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u32 pll2denom;
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u32 pll2num;
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u32 pll2ss;
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u32 rsvd10[55];
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u32 pll3csr;
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u32 pll3div_vco;
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u32 pll3div_pfd0;
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u32 pll3div_pfd1;
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u32 pll3cfg;
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u32 pll3pfdcfg;
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u32 pll3denom;
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u32 pll3num;
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u32 pll3ss;
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u32 pll3lock;
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u32 rsvd11[54];
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u32 enetstamp;
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u32 rsvd12[67];
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u32 pllusbcfg;
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u32 rsvd13[59];
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u32 aud_clk1;
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u32 sai5_4_clk;
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u32 tpm6_7clk;
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u32 mqs1clk;
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u32 rsvd14[60];
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u32 lvdscfg;
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};
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struct cgc2_regs {
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u32 verid;
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u32 rsvd1[4];
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u32 hificlk;
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u32 rsvd2[2];
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u32 clkoutcfg;
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u32 rsvd3[6];
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u32 niclpavclk;
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u32 ddrclk;
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u32 rsvd4[19];
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u32 clkdivrst;
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u32 rsvd5[29];
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u32 soscdiv;
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u32 rsvd6[63];
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u32 frodiv;
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u32 rsvd7[253];
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u32 pll4csr;
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u32 pll4div_vco;
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u32 pll4div_pfd0;
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u32 pll4div_pfd1;
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u32 pll4cfg;
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u32 pll4pfdcfg;
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u32 pll4denom;
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u32 pll4num;
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u32 pll4ss;
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u32 pll4lock;
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u32 rsvd8[128];
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u32 aud_clk2;
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u32 sai7_6_clk;
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u32 tpm8clk;
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u32 rsvd9[1];
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u32 spdifclk;
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u32 rsvd10[59];
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u32 lvdscfg;
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};
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u32 cgc_clk_get_rate(enum cgc_clk clk);
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void cgc1_pll3_init(ulong freq);
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void cgc1_pll2_init(ulong freq);
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void cgc1_soscdiv_init(void);
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void cgc1_init_core_clk(ulong freq);
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void cgc2_pll4_init(bool pll4_reset);
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void cgc2_ddrclk_config(u32 src, u32 div);
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void cgc2_ddrclk_wait_unlock(void);
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u32 cgc1_sosc_div(enum cgc_clk clk);
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void cgc1_enet_stamp_sel(u32 clk_src);
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void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);
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void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div);
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void cgc2_lpav_init(enum cgc_clk clk);
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#endif
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