60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR4_MPR_PDA_IF_H
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#define _MV_DDR4_MPR_PDA_IF_H
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#include "ddr3_init.h"
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#include "mv_ddr_common.h"
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#define MV_DDR4_VREF_STEP_SIZE 3
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#define MV_DDR4_VREF_MIN_RANGE 1
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#define MV_DDR4_VREF_MAX_RANGE 73
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#define MV_DDR4_VREF_MAX_COUNT (((MV_DDR4_VREF_MAX_RANGE - MV_DDR4_VREF_MIN_RANGE) / MV_DDR4_VREF_STEP_SIZE) + 2)
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#define MV_DDR4_MPR_READ_PATTERN_NUM 3
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enum mv_ddr4_mpr_read_format {
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MV_DDR4_MPR_READ_SERIAL,
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MV_DDR4_MPR_READ_PARALLEL,
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MV_DDR4_MPR_READ_STAGGERED,
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MV_DDR4_MPR_READ_RSVD_TEMP
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};
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enum mv_ddr4_mpr_read_type {
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MV_DDR4_MPR_READ_RAW,
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MV_DDR4_MPR_READ_DECODED
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};
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enum mv_ddr4_vref_tap_state {
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MV_DDR4_VREF_TAP_START,
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MV_DDR4_VREF_TAP_BUSY,
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MV_DDR4_VREF_TAP_FLIP,
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MV_DDR4_VREF_TAP_END
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};
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int mv_ddr4_mode_regs_init(u8 dev_num);
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int mv_ddr4_mpr_read(u8 dev_num, u32 mpr_num, u32 page_num,
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enum mv_ddr4_mpr_read_format read_format,
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enum mv_ddr4_mpr_read_type read_type,
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u32 *data);
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int mv_ddr4_mpr_write(u8 dev_num, u32 mpr_location, u32 mpr_num,
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u32 page_num, u32 data);
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int mv_ddr4_dq_pins_mapping(u8 dev_num);
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int mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id,
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enum hws_access_type access_type,
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int enable);
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int mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id,
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enum hws_access_type access_type,
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u32 taps_num,
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enum mv_ddr4_vref_tap_state state);
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int mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type,
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u32 range, u32 vdq_tv, u8 vdq_training_ena);
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int mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, u32 subphy_mask, u32 cs_num);
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int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
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#endif /* _MV_DDR4_MPR_PDA_IF_H */
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