27 lines
776 B
C
27 lines
776 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR4_TRAINING_CALIBRATION_H
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#define _MV_DDR4_TRAINING_CALIBRATION_H
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/* vref subphy calibration state */
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enum mv_ddr4_vref_subphy_cal_state {
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MV_DDR4_VREF_SUBPHY_CAL_ABOVE,
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MV_DDR4_VREF_SUBPHY_CAL_UNDER,
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MV_DDR4_VREF_SUBPHY_CAL_INSIDE,
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MV_DDR4_VREF_SUBPHY_CAL_END
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};
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/* calibrate DDR4 dq vref (tx) */
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int mv_ddr4_dq_vref_calibration(u8 dev_num, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS]);
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/* calibrate receiver (receiver duty cycle) */
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int mv_ddr4_receiver_calibration(u8 dev_num);
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/* tune dm signal */
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int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS]);
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#endif /* _MV_DDR4_TRAINING_CALIBRATION_H */
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