65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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*/
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#ifndef __MICROCHIP_DDR2_TIMING_H
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#define __MICROCHIP_DDR2_TIMING_H
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/* MPLL freq is 400MHz */
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#define T_CK 2500 /* 2500 psec */
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#define T_CK_CTRL (T_CK * 2)
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/* Burst length in cycles */
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#define BL 2
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/* default CAS latency for all speed grades */
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#define RL 5
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/* default write latency for all speed grades = CL-1 */
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#define WL 4
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/* From Micron MT47H64M16HR-3 data sheet */
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#define T_RFC_MIN 127500 /* psec */
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#define T_WR 15000 /* psec */
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#define T_RP 12500 /* psec */
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#define T_RCD 12500 /* psec */
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#define T_RRD 7500 /* psec */
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/* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */
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#define T_RRD_TCK 2
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#define T_WTR 7500 /* psec */
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/* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */
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#define T_WTR_TCK 2
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#define T_RTP 7500 /* psec */
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#define T_RTP_TCK (BL / 2)
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#define T_XP_TCK 2 /* clocks */
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#define T_CKE_TCK 3 /* clocks */
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#define T_XSNR (T_RFC_MIN + 10000) /* psec */
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#define T_DLLK 200 /* clocks */
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#define T_RAS_MIN 45000 /* psec */
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#define T_RC 57500 /* psec */
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#define T_FAW 35000 /* psec */
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#define T_MRD_TCK 2 /* clocks */
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#define T_RFI 7800000 /* psec */
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/* DDR Addressing */
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#define COL_BITS 10
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#define BA_BITS 3
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#define ROW_BITS 13
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#define CS_BITS 1
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/* DDR Addressing scheme: {CS, ROW, BA, COL} */
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#define COL_HI_RSHFT 0
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#define COL_HI_MASK 0
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#define COL_LO_MASK ((1 << COL_BITS) - 1)
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#define BA_RSHFT COL_BITS
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#define BA_MASK ((1 << BA_BITS) - 1)
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#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS)
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#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1)
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#define CS_ADDR_RSHIFT 0
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#define CS_ADDR_MASK 0
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#endif /* __MICROCHIP_DDR2_TIMING_H */
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