e9fc3d4f62
commit 3d0f2e37c57b0d2f60e0b985d7006220d94bd9b0 upstream. The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> |
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| Kconfig | ||
| Makefile | ||
| phy-j721e-wiz.c | ||