25 lines
587 B
C
25 lines
587 B
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_J721E_H
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#define LPDDR4_J721E_H
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#include "lpddr4_j721e_ctl_regs_rw_masks.h"
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#define DSLICE_NUM (4U)
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#define ASLICE_NUM (1U)
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#define DSLICE0_REG_COUNT (140U)
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#define DSLICE1_REG_COUNT (140U)
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#define DSLICE2_REG_COUNT (140U)
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#define DSLICE3_REG_COUNT (140U)
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#define ASLICE0_REG_COUNT (52U)
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#define PHY_CORE_REG_COUNT (140U)
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#endif /* LPDDR4_J721E_H */
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