Lukasz Majewski dc619924c7 ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code ... This patch extends the vf610 DDR memory controller code to support SW leveling. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>		2019-02-15 12:16:50 +01:00
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arc	ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGN	2019-01-25 08:41:09 +03:00
arm	ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup code	2019-02-15 12:16:50 +01:00
m68k	…
microblaze	…
mips	dt: bcm6838: add watchdog	2019-02-09 07:50:50 -05:00
nds32	nds32: dts: Fix mmc node compatible string	2019-01-22 17:36:20 +08:00
nios2	…
powerpc	linker: Modify linker scripts to be more generic	2019-01-26 22:55:53 -05:00
riscv	riscv: qemu: define standalone load address	2019-01-15 09:36:31 +08:00
sandbox	Fix recent changes to serial API for driver model	2019-01-15 22:05:34 -05:00
sh	sh: bitops: add hweight*() macros	2019-02-07 15:33:21 +05:30
x86	x86: do not use i386 code for x86_64 memory functions	2019-02-13 09:40:06 +01:00
xtensa	…
.gitignore	…
Kconfig	dm: sound: Create an option to use driver model for sound	2018-12-13 16:32:49 -07:00