105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/sections.h>
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define IMEM_LEN 32768//23400 //byte
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#define DMEM_LEN 16384//1720 //byte
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#define IMEM_2D_OFFSET 49152
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#define IMEM_OFFSET_ADDR 0x00050000
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#define DMEM_OFFSET_ADDR 0x00054000
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#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
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/* We need PHY iMEM PHY is 32KB padded */
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void ddr_load_train_code(enum fw_type type)
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{
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u32 tmp32, i;
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u32 error = 0;
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unsigned long pr_to32, pr_from32;
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unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
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unsigned long imem_start = (unsigned long)&_end + fw_offset;
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unsigned long dmem_start = imem_start + IMEM_LEN;
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pr_from32 = imem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
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for(i = 0x0; i < IMEM_LEN; ){
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tmp32 = readl(pr_from32);
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writew(tmp32 & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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pr_from32 += 4;
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i += 4;
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}
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pr_from32 = dmem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
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for(i = 0x0; i < DMEM_LEN;){
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tmp32 = readl(pr_from32);
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writew(tmp32 & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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pr_from32 += 4;
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i += 4;
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}
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printf("check ddr4_pmu_train_imem code\n");
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pr_from32 = imem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
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for(i = 0x0; i < IMEM_LEN;){
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tmp32 = (readw(pr_to32) & 0x0000ffff);
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pr_to32 += 4;
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tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
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if(tmp32 != readl(pr_from32)){
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printf("%lx %lx\n", pr_from32, pr_to32);
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error++;
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}
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pr_from32 += 4;
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pr_to32 += 4;
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i += 4;
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}
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if(error){
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printf("check ddr4_pmu_train_imem code fail=%d\n",error);
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}else{
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printf("check ddr4_pmu_train_imem code pass\n");
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}
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printf("check ddr4_pmu_train_dmem code\n");
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pr_from32 = dmem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
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for(i = 0x0; i < DMEM_LEN;){
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tmp32 = (readw(pr_to32) & 0x0000ffff);
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pr_to32 += 4;
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tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
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if(tmp32 != readl(pr_from32)){
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printf("%lx %lx\n", pr_from32, pr_to32);
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error++;
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}
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pr_from32 += 4;
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pr_to32 += 4;
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i += 4;
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}
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if(error){
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printf("check ddr4_pmu_train_dmem code fail=%d",error);
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}else{
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printf("check ddr4_pmu_train_dmem code pass\n");
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}
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}
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