361 lines
7.5 KiB
C
361 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SH QSPI (Quad SPI) driver
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*/
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#include <common.h>
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#include <console.h>
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#include <malloc.h>
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#include <spi.h>
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#include <wait_bit.h>
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#include <asm/arch/rmobile.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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/* SH QSPI register bit masks <REG>_<BIT> */
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#define SPCR_MSTR 0x08
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#define SPCR_SPE 0x40
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#define SPSR_SPRFF 0x80
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#define SPSR_SPTEF 0x20
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#define SPPCR_IO3FV 0x04
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#define SPPCR_IO2FV 0x02
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#define SPPCR_IO1FV 0x01
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#define SPBDCR_RXBC0 BIT(0)
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#define SPCMD_SCKDEN BIT(15)
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#define SPCMD_SLNDEN BIT(14)
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#define SPCMD_SPNDEN BIT(13)
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#define SPCMD_SSLKP BIT(7)
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#define SPCMD_BRDV0 BIT(2)
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#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
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SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPBFCR_TXRST BIT(7)
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#define SPBFCR_RXRST BIT(6)
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#define SPBFCR_TXTRG 0x30
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#define SPBFCR_RXTRG 0x07
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/* SH QSPI register set */
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struct sh_qspi_regs {
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u8 spcr;
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u8 sslp;
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u8 sppcr;
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u8 spsr;
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u32 spdr;
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u8 spscr;
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u8 spssr;
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u8 spbr;
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u8 spdcr;
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u8 spckd;
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u8 sslnd;
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u8 spnd;
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u8 dummy0;
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u16 spcmd0;
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u16 spcmd1;
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u16 spcmd2;
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u16 spcmd3;
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u8 spbfcr;
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u8 dummy1;
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u16 spbdcr;
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u32 spbmul0;
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u32 spbmul1;
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u32 spbmul2;
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u32 spbmul3;
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};
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struct sh_qspi_slave {
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#if !CONFIG_IS_ENABLED(DM_SPI)
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struct spi_slave slave;
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#endif
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struct sh_qspi_regs *regs;
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};
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static void sh_qspi_init(struct sh_qspi_slave *ss)
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{
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/* QSPI initialize */
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/* Set master mode only */
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writeb(SPCR_MSTR, &ss->regs->spcr);
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/* Set SSL signal level */
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writeb(0x00, &ss->regs->sslp);
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/* Set MOSI signal value when transfer is in idle state */
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writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
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/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
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writeb(0x01, &ss->regs->spbr);
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/* Disable Dummy Data Transmission */
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writeb(0x00, &ss->regs->spdcr);
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/* Set clock delay value */
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writeb(0x00, &ss->regs->spckd);
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/* Set SSL negation delay value */
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writeb(0x00, &ss->regs->sslnd);
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/* Set next-access delay value */
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writeb(0x00, &ss->regs->spnd);
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/* Set equence command */
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writew(SPCMD_INIT2, &ss->regs->spcmd0);
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/* Reset transfer and receive Buffer */
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setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Clear transfer and receive Buffer control bit */
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clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Set equence control method. Use equence0 only */
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writeb(0x00, &ss->regs->spscr);
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/* Enable SPI function */
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setbits_8(&ss->regs->spcr, SPCR_SPE);
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}
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static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
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{
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/* Set master mode only */
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writeb(SPCR_MSTR, &ss->regs->spcr);
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/* Set command */
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writew(SPCMD_INIT1, &ss->regs->spcmd0);
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/* Reset transfer and receive Buffer */
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setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Clear transfer and receive Buffer control bit */
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clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Set equence control method. Use equence0 only */
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writeb(0x00, &ss->regs->spscr);
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/* Enable SPI function */
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setbits_8(&ss->regs->spcr, SPCR_SPE);
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}
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static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
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{
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/* Disable SPI Function */
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clrbits_8(&ss->regs->spcr, SPCR_SPE);
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}
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static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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u32 nbyte, chunk;
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int i, ret = 0;
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u8 dtdata = 0, drdata;
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u8 *tdata = &dtdata, *rdata = &drdata;
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u32 *spbmul0 = &ss->regs->spbmul0;
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if (dout == NULL && din == NULL) {
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if (flags & SPI_XFER_END)
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sh_qspi_cs_deactivate(ss);
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return 0;
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}
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if (bitlen % 8) {
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printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
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return 1;
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}
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nbyte = bitlen / 8;
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if (flags & SPI_XFER_BEGIN) {
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sh_qspi_cs_activate(ss);
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/* Set 1048576 byte */
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writel(0x100000, spbmul0);
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}
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if (flags & SPI_XFER_END)
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writel(nbyte, spbmul0);
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if (dout != NULL)
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tdata = (u8 *)dout;
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if (din != NULL)
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rdata = din;
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while (nbyte > 0) {
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/*
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* Check if there is 32 Byte chunk and if there is, transfer
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* it in one burst, otherwise transfer on byte-by-byte basis.
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*/
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chunk = (nbyte >= 32) ? 32 : 1;
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clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
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chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
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ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
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true, 1000, true);
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if (ret)
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return ret;
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for (i = 0; i < chunk; i++) {
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writeb(*tdata, &ss->regs->spdr);
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if (dout != NULL)
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tdata++;
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}
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ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
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true, 1000, true);
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if (ret)
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return ret;
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for (i = 0; i < chunk; i++) {
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*rdata = readb(&ss->regs->spdr);
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if (din != NULL)
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rdata++;
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}
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nbyte -= chunk;
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}
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if (flags & SPI_XFER_END)
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sh_qspi_cs_deactivate(ss);
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return ret;
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
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{
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return container_of(slave, struct sh_qspi_slave, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct sh_qspi_slave *ss = to_sh_qspi(slave);
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sh_qspi_cs_activate(ss);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct sh_qspi_slave *ss = to_sh_qspi(slave);
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sh_qspi_cs_deactivate(ss);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct sh_qspi_slave *ss;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
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if (!ss) {
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printf("SPI_error: Fail to allocate sh_qspi_slave\n");
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return NULL;
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}
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ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
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/* Init SH QSPI */
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sh_qspi_init(ss);
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return &ss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct sh_qspi_slave *spi = to_sh_qspi(slave);
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free(spi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct sh_qspi_slave *ss = to_sh_qspi(slave);
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return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
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}
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#else
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#include <dm.h>
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static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct sh_qspi_slave *ss = dev_get_platdata(bus);
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return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
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}
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static int sh_qspi_set_speed(struct udevice *dev, uint speed)
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{
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/* This is a SPI NOR controller, do nothing. */
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return 0;
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}
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static int sh_qspi_set_mode(struct udevice *dev, uint mode)
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{
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/* This is a SPI NOR controller, do nothing. */
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return 0;
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}
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static int sh_qspi_probe(struct udevice *dev)
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{
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struct sh_qspi_slave *ss = dev_get_platdata(dev);
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sh_qspi_init(ss);
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return 0;
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}
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static int sh_qspi_ofdata_to_platdata(struct udevice *dev)
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{
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struct sh_qspi_slave *plat = dev_get_platdata(dev);
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plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
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return 0;
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}
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static const struct dm_spi_ops sh_qspi_ops = {
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.xfer = sh_qspi_xfer,
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.set_speed = sh_qspi_set_speed,
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.set_mode = sh_qspi_set_mode,
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};
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static const struct udevice_id sh_qspi_ids[] = {
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{ .compatible = "renesas,qspi" },
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{ }
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};
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U_BOOT_DRIVER(sh_qspi) = {
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.name = "sh_qspi",
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.id = UCLASS_SPI,
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.of_match = sh_qspi_ids,
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.ops = &sh_qspi_ops,
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.ofdata_to_platdata = sh_qspi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct sh_qspi_slave),
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.probe = sh_qspi_probe,
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};
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#endif
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