70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PIO interface for QFW
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*
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* (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
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* (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
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*/
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#define LOG_CATEGORY UCLASS_QFW
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#include <asm/io.h>
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#include <dm/device.h>
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#include <qfw.h>
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/*
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* PIO ports are correct for x86, which appears to be the only arch that uses
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* PIO.
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*/
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#define FW_CONTROL_PORT 0x510
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#define FW_DATA_PORT 0x511
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#define FW_DMA_PORT_LOW 0x514
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#define FW_DMA_PORT_HIGH 0x518
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static void qfw_pio_read_entry_io(struct udevice *dev, u16 entry, u32 size,
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void *address)
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{
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/*
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* writing FW_CFG_INVALID will cause read operation to resume at last
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* offset, otherwise read will start at offset 0
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*
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* Note: on platform where the control register is IO port, the
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* endianness is little endian.
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*/
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if (entry != FW_CFG_INVALID)
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outw(cpu_to_le16(entry), FW_CONTROL_PORT);
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/* the endianness of data register is string-preserving */
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u32 i = 0;
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u8 *data = address;
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while (size--)
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data[i++] = inb(FW_DATA_PORT);
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}
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/* Read configuration item using fw_cfg DMA interface */
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static void qfw_pio_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
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{
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/* the DMA address register is big-endian */
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outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
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while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR);
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}
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static int qfw_pio_probe(struct udevice *dev)
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{
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return qfw_register(dev);
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}
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static struct dm_qfw_ops qfw_pio_ops = {
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.read_entry_io = qfw_pio_read_entry_io,
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.read_entry_dma = qfw_pio_read_entry_dma,
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};
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U_BOOT_DRIVER(qfw_pio) = {
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.name = "qfw_pio",
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.id = UCLASS_QFW,
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.probe = qfw_pio_probe,
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.ops = &qfw_pio_ops,
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};
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