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u-boot/arch/riscv/cpu
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Trevor Woerner 1001502545 CONFIG_SPL_SYS_[DI]CACHE_OFF: add 
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
 		2019-05-18 08:15:35 -04:00
..
ax25 CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
generic riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems 2019-02-27 09:12:33 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
cpu.c riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled 2019-05-09 16:46:46 +08:00
mtrap.S riscv: Return to previous privilege level after trap handling 2018-12-18 09:56:27 +08:00
start.S riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled 2019-05-09 16:46:46 +08:00
u-boot.lds riscv: Make start.S available for all targets 2018-10-03 17:48:14 +08:00