Bai Ping 65fed31a52 MLK-19777-03: imx8mm_evk: Optimize the ddr4 init flow ... Optimize the DDR4 init flow. Split the common flow with the DDR specific timing config. So the common flow can be reused. Signed-off-by: Bai Ping <ping.bai@nxp.com>		2018-10-01 17:25:25 +08:00
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altera	ddr: altera: silence PHY calibration unless in debug mode	2018-01-25 09:59:37 +01:00
fsl	Revert "drivers/ddr/fsl: Dual-license DDR driver"	2018-02-14 21:34:05 -05:00
imx8m	MLK-19777-03: imx8mm_evk: Optimize the ddr4 init flow	2018-10-01 17:25:25 +08:00
marvell	ddr: marvell: update ddr controller init and freq	2018-01-19 16:30:29 +01:00
microchip	wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2018-01-24 12:03:43 +05:30
Kconfig	arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig	2017-04-14 14:06:57 +02:00