80 lines
2.7 KiB
C
80 lines
2.7 KiB
C
/*
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include "ddr4_define.h"
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extern unsigned int mr_value[3][7];
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void dwc_ddrphy_phyinit_userCustom_E_setDfiClk (unsigned int pstate) {
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if (pstate == 1) {
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ddr_dbg("C: pstate1 ...\n");
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#ifdef PLLBYPASS_250MBPS
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dram_enable_bypass(DRAM_BYPASSCLK_250M);
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#endif
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#ifdef PLLBYPASS_400MBPS
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dram_enable_bypass(DRAM_BYPASSCLK_400M);
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#endif
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} else if (pstate == 2) {
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ddr_dbg("C: pstate2 ...\n");
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dram_enable_bypass(DRAM_BYPASSCLK_100M);
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} else {
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ddr_dbg("C: pstate0 ...\n");
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dram_pll_init(DRAM_PLL_OUT_600M);
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dram_disable_bypass();
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}
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}
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void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void)
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{
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wait_ddrphy_training_complete();
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}
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void dwc_ddrphy_phyinit_userCustom_overrideUserInput (void) {}
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void dwc_ddrphy_phyinit_userCustom_A_bringupPower (void) {}
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void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy (void) {}
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void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned int Train2D) {}
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void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) {}
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void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void) {}
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void ddr4_mr_write(unsigned int mr, unsigned int data, unsigned int read, unsigned int rank)
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{
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unsigned int tmp, mr_mirror, data_mirror;
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/* 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there is no outstanding MR transaction. No */
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/* writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. */
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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/* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and (for MRWs) */
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/* MRCTRL1.mr_data to define the MR transaction. */
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/* (A3, A4), (A5, A6), (A7, A8), (BA0, BA1), (A11, A13), */
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tmp = reg32_read(DDRC_DIMMCTL(0));
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if ((tmp & 0x2) && (rank == 0x2)) {
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mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1);/* BA0, BA1 swap */
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data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) |
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((data & 0x40) >> 1) | ((data & 0x80) << 1) | ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ;
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} else {
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mr_mirror = mr;
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data_mirror = data;
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}
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reg32_write(DDRC_MRCTRL0(0), read | (mr_mirror << 12) | (rank << 4));
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reg32_write(DDRC_MRCTRL1(0), data_mirror);
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/* 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. This bit is self-clearing, and triggers */
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/* the MR transaction. The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs the MR */
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/* transaction to SDRAM, and no further accesses can be initiated until it is deasserted. */
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reg32setbit(DDRC_MRCTRL0(0), 31);
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp);
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}
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