163 lines
3.2 KiB
C
163 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <efi_loader.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region apple_mem_map[] = {
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{
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/* I/O */
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.virt = 0x200000000,
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.phys = 0x200000000,
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.size = 8UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x500000000,
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.phys = 0x500000000,
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.size = 2UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x680000000,
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.phys = 0x680000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x6a0000000,
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.phys = 0x6a0000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x6c0000000,
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.phys = 0x6c0000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x800000000,
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.phys = 0x800000000,
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.size = 8UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Empty entry for framebuffer */
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0,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = apple_mem_map;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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ofnode node;
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int index, ret;
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fdt_addr_t base;
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fdt_size_t size;
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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return ret;
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/* Update RAM mapping */
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index = ARRAY_SIZE(apple_mem_map) - 3;
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apple_mem_map[index].virt = gd->ram_base;
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apple_mem_map[index].phys = gd->ram_base;
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apple_mem_map[index].size = gd->ram_size;
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node = ofnode_path("/chosen/framebuffer");
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if (!ofnode_valid(node))
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return 0;
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base = ofnode_get_addr_size(node, "reg", &size);
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if (base == FDT_ADDR_T_NONE)
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return 0;
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/* Add framebuffer mapping */
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index = ARRAY_SIZE(apple_mem_map) - 2;
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apple_mem_map[index].virt = base;
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apple_mem_map[index].phys = base;
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apple_mem_map[index].size = size;
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apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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return 0;
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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#define APPLE_WDT_BASE 0x23d2b0000ULL
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#define APPLE_WDT_SYS_CTL_ENABLE BIT(2)
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typedef struct apple_wdt {
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u32 reserved0[3];
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u32 chip_ctl;
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u32 sys_tmr;
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u32 sys_cmp;
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u32 reserved1;
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u32 sys_ctl;
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} apple_wdt_t;
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void reset_cpu(void)
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{
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apple_wdt_t *wdt = (apple_wdt_t *)APPLE_WDT_BASE;
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writel(0, &wdt->sys_cmp);
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writel(APPLE_WDT_SYS_CTL_ENABLE, &wdt->sys_ctl);
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while(1)
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wfi();
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}
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extern long fw_dtb_pointer;
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void *board_fdt_blob_setup(int *err)
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{
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/* Return DTB pointer passed by m1n1 */
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*err = 0;
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return (void *)fw_dtb_pointer;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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/*
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* Top part of RAM is used by firmware for things like the
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* framebuffer. This gives us plenty of room to play with.
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*/
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return 0x980000000;
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}
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